GL-S MirrorBit® Eclipse™ Flash Non-Volatile Memory Family IS29GL01GS IS29GL512S IS29GL256S IS29GL128S 1 Gbit 512 Mbit 256 Mbit 128 Mbit (128 Mbyte) (64 Mbyte) (32 Mbyte) (16 Mbyte) GL-S MirrorBit® Family Cover Sheet CMOS 3.
D at a S hee t Copyright © 2015 Integrated Silicon Solution, All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
GL-S MirrorBit® Eclipse™ Flash Non-Volatile Memory Family IS29GL01GS IS29GL512S IS29GL256S IS29GL128S 1 Gbit 512 Mbit 256 Mbit 128 Mbit (128 Mbyte) (64 Mbyte) (32 Mbyte) (16 Mbyte) CMOS 3.0 Volt Core with Versatile I/O Data Sheet General Description The ISSI IS29GL01G/512/256/128S are MirrorBit Eclipse flash products fabricated on 65 nm process technology. These devices offer a fast page access time as fast as 15 ns with a corresponding random access time as fast as 90 ns.
D at a S hee t Performance Summary Maximum Read Access Times Density 128 Mb 256 Mb 512 Mb 1 Gb Random Access Time (tACC) Voltage Range Page Access Time (tPACC) CE# Access Time (tCE) OE# Access Time (tOE) Full VCC= VIO 90 15 90 25 VersatileIO VIO 100 25 100 35 Full VCC= VIO 90 15 90 25 VersatileIO VIO 100 25 100 35 Full VCC= VIO 100 15 100 25 VersatileIO VIO 110 25 110 35 Full VCC= VIO 100 15 100 25 VersatileIO VIO 110 25 110 35 Typical Program and Erase Rat
Data She et Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Performance Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.
D at a 10.3 10.4 6 S hee t Power-On Reset (POR) and Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11. Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 56-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data She et Figures Figure 1.1 Figure 3.1 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 10.6 Figure 10.7 Figure 10.8 Figure 10.9 Figure 10.10 Figure 10.11 Figure 10.12 Figure 10.13 Figure 10.14 Figure 10.15 Figure 10.16 Figure 10.17 Figure 10.18 Figure 10.19 Figure 10.20 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Block Diagram . . . . . . . . . . . . . . . .
D at a S hee t Tables Table 1.1 Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.5 Table 2.6 Table 3.1 Table 3.2 Table 5.1 Table 5.2 Table 5.3 Table 5.4 Table 5.5 Table 5.6 Table 5.7 Table 5.8 Table 5.9 Table 5.10 Table 5.11 Table 5.12 Table 5.13 Table 5.14 Table 5.15 Table 5.16 Table 5.17 Table 5.18 Table 5.19 Table 5.20 Table 5.21 Table 5.22 Table 5.23 Table 5.24 Table 5.25 Table 5.26 Table 6.1 Table 6.2 Table 6.3 Table 6.4 Table 6.5 Table 6.6 Table 7.1 Table 8.1 Table 9.1 Table 9.2 Table 9.3 Table 9.
Data Table 10.7 Table 10.8 Table 10.9 Table 13.1 She et Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate CE# Controlled Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS29GL-S Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . .
D at a 1. S hee t Product Overview The GL-S family consists of 128-Mbit to 1Gbit, 3.0V core, Versatile I/O, non-volatile, flash memory devices. These devices have a 16-bit (word) wide data bus and use only word boundary addresses. All read accesses provide 16 bits of data on each bus transfer cycle. All writes take 16 bits of data from each bus transfer cycle. Figure 1.
Data She et Table 1.1 IS29GL-S Address Map Type Count Addresses Address within Page 16 A3 - A0 Address within Write Buffer 256 A7 - A0 Page 4096 A15 - A4 Write-Buffer-Line 256 A15 - A8 1024 (1 Gb) 512 (512 Mb) Sector 256 (256 Mb) AMAX - A16 128 (128 Mb) The device control logic is subdivided into two parallel operating sections, the Host Interface Controller (HIC) and the Embedded Algorithm Controller (EAC).
D at a S hee t Software Interface 2. Address Space Maps There are several separate address spaces that may appear within the address range of the flash memory device. One address space is visible (entered) at any given time. Flash Memory Array: the main non-volatile memory array used for storage of data that may be randomly accessed by asynchronous read operations. ID/CFI: a memory array used for ISSI factory programmed device characteristics information.
Data She et While in EA mode, only a Program / Erase suspend command or the Status Register Read command will be accepted. All other commands are ignored. Thus, no other ASO may be entered from the EA mode. When an Embedded Algorithm is suspended, the Data Polling ASO is visible until the device has suspended the EA. When the EA is suspended the Data Polling ASO is exited and Flash Array data is available.
D at a S hee t Table 2.
Data 2.2.1 She et Device ID The Joint Electron Device Engineering Council (JEDEC) standard JEP106T defines the manufacturer ID for a compliant memory. Common industry usage defined a method and format for reading the manufacturer ID and a device specific ID from a memory device. The manufacturer and device ID information is primarily intended for programming equipment to automatically match a device with the corresponding programming algorithm.
D at a 2.4 S hee t Data Polling Status ASO The Data Polling Status ASO contains a single word of volatile memory indicating the progress of an EA. The Data Polling Status ASO is entered immediately following the last write cycle of any command sequence that initiates an EA.
Data 2.6 2.6.1 She et Sector Protection Control Lock Register ASO The Lock register ASO contains a single word of OTP memory. When the ASO is entered the Lock Register appears at all word locations in the device address space. However, it is recommended to read or program the Lock Register only at location 0 of the device address space for future compatibility. 2.6.2 Persistent Protection Bits (PPB) ASO The PPB ASO contains one bit of a Flash Memory Array for each Sector in the device.
D at a 3. S hee t Data Protection The device offers several features to prevent malicious or accidental modification of any sector via hardware means. 3.1 3.1.1 Device Protection Methods Power-Up Write Inhibit RESET#, CE#, WE#, and, OE# are ignored during Power-On Reset (POR). During POR, the device can not be selected, will not accept commands on the rising edge of WE#, and does not drive outputs.
Data 3.4 3.4.1 She et Sector Protection Methods Write Protect Signal If WP# = VIL, the lowest or highest address sector is protected from program or erase operations independent of any other ASP configuration. Whether it is the lowest or highest sector depends on the device ordering option (model) selected. If WP# = VIH, the lowest or highest address sector is not protected by the WP# signal but it may be protected by other aspects of ASP configuration.
D at a S hee t There is no command in the Persistent Protection method to set the PPB Lock bit therefore the PPB Lock bit will remain at 0 until the next power-off or hardware reset. The Persistent Protection method allows boot code the option of changing sector protection by programming or erasing the PPB, then protecting the PPB from further change for the remainder of normal system operation by clearing the PPB Lock bit. This is sometimes called Boot-code controlled sector protection.
Data 3.4.6 She et Sector Protection States Summary Each sector can be in one of the following protection states: Unlocked – The sector is unprotected and protection can be changed by a simple command. The protection state defaults to unprotected after a power cycle or hardware reset. Dynamically Locked – A sector is protected and protection can be changed by a simple command. The protection state is not saved across a power cycle or hardware reset.
D at a S hee t If both lock bits are selected to be programmed at the same time, the operation will abort. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled. If the password mode is to be chosen, the password must be programmed prior to setting the corresponding lock register bit.
Data She et The specific address and data are compared after the Program Buffer To Flash command has been given. If they don't match to the internal set value than the status register will return to the ready state with the Program Status Bit set to 1 and Program Status Register Bit set to 1 indicating a failed programming operation. It is a failure to change the state of the PPB Lock bit because it is still protected by the lack of a valid password.
D at a 4. 4.1 S hee t Read Operations Asynchronous Read Each read access may be made to any location in the memory (random access). Each random access is selftimed with the same latency from CE# or address to valid data (tACC or tCE). 4.2 Page Mode Read Each random read accesses an entire 32-byte Page in parallel. Subsequent reads within the same Page have faster read access speed.
Data 5. She et Embedded Operations 5.1 Embedded Algorithm Controller (EAC) The EAC takes commands from the host system for programming and erasing the flash memory array and performs all the complex operations needed to change the non-volatile memory state. This frees the host system from any need to manage the program and erase processes. There are four EAC operation categories: Standby (Read Mode) Address Space Switching Embedded Algorithms (EA) Advanced Sector Protection (ASP) Management 5.
D at a 5.2 S hee t Program and Erase Summary Flash data bits are erased in parallel in a large group called a sector. The Erase operation places each data bit in the sector in the logical 1 state (High). Flash data bits may be individually programmed from the erased 1 state to the programmed logical 0 (low) state. A data bit of 0 cannot be programmed back to a 1. A succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1.
Data She et overhead in writing program commands and reduces memory device internal overhead in programming operations to make Write Buffer Programming more efficient and thus faster than programming individual words with the Word Programming command. 5.2.2 Incremental Programming The same word location may be programmed more than once, by either the Word or Write Buffer Programming methods, to incrementally change 1’s to 0’s. 5.3 Command Set 5.3.1 5.3.1.
D at a 5.3.1.2 S hee t Write Buffer Programming A write buffer is used to program data within a 512-byte address range aligned on a 512-byte boundary (Line). Thus, a full Write Buffer Programming operation must be aligned on a Line boundary. Programming operations of less than a full 512 bytes may start on any word boundary but may not cross a Line boundary.
Data She et with invalid or unstable data values. In this case the same area will need to be reprogrammed with the same data or erased to ensure data values are properly programmed or erased. Figure 5.2 Write Buffer Programming Operation with Data Polling Status Write “Write to Buffer” command Sector Address Write “Word Count” to program - 1 (WC) Sector Address Write Starting Address/Data Yes WC = 0? Write to a different Sector Address No ABORT Write to Buffer Operation? Yes Write to Buffer ABORTED.
D at a S hee t Figure 5.3 Write Buffer Programming Operation with Status Register Write “Write to Buffer” command Sector Address Write “Word Count” to program - 1 (WC) Sector Address Write Starting Address/Data Yes WC = 0? Write to a different Sector Address No ABORT Write to Buffer Operation? Yes Write to Buffer ABORTED. Must write “Write-to-Buffer ABORT RESET” command sequence to return to READ mode.
Data She et Table 5.1 Write Buffer Programming Command Sequence Sequence Address Data Comment Issue Unlock Command 1 555/AAA AA Issue Unlock Command 2 2AA/555 55 Issue Write to Buffer Command at Sector Address SA 0025h Issue Number of Locations at Sector Address SA WC WC = number of words to program - 1 Starting Address PD Selects Write-Buffer-Page and loads first Address/Data Pair.
D at a S hee t Program operations can be interrupted as often as necessary but in order for a program operation to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to tPRS in Embedded Algorithm Controller (EAC) on page 25. Program suspend and resume is not supported while entered in an ASO. While in program suspend entry into ASO is not supported. 5.3.
Data 5.3.4.2 She et Sector Erase The sector erase function erases one sector in the memory array. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire sector for an all 0 data pattern prior to electrical erase. After a successful sector erase, all locations within the erased sector contain FFFFh. The system is not required to provide any controls or timings during these operations.
D at a 5.3.5 S hee t Erase Suspend / Erase Resume The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, the main flash array. This command is valid only during sector erase or program operation. The Erase Suspend command is ignored if written during the chip erase operation.
Data 5.3.6 5.3.6.1 She et ASO Entry and Exit ID-CFI ASO The system can access the ID-CFI ASO by issuing the ID-CFI Entry command sequence during Read Mode. This entry command uses the Sector Address (SA) in the command to determine which sector will be overlaid and which sector's protection state is reported in word location 2h. See the detail description Table 6.2 on page 60. The ID-CFI ASO allows the following activities: Read ID-CFI ASO, using the same SA as used in the entry command.
D at a 5.3.6.4 S hee t Lock Register ASO The system can access the Lock Register by issuing the Lock Register entry command sequence during Read Mode. This entry command does not use a sector address from the entry command. The Lock Register appears at word location 0 in the device address space. All other locations in the device address space are undefined. The Lock Register ASO allows the following activities: Read Lock Register, using device address location 0.
Data 5.3.6.8 She et DYB ASO The system can access the DYB ASO by issuing the DYB entry command sequence during Read Mode. This entry command does not use a sector address from the entry command. The DYB bit for a sector appears in bit 0 of all word locations in the sector. The DYB ASO allows the following activities: Read DYB protection status of a sector in bit 0 of any word in the sector. Set the DYB bit using a modified Word Programming command.
D at a S hee t Program Suspended (bit 2), The current state bits indicate whether an EA is in process, suspended, or completed. The upper 8 bits (bits 15:8) are reserved. These have undefined High or Low value that can change from one status read to another. These bits should be treated as don't care and ignored by any software reading status. The Soft Reset Command will clear to 0 bits [5, 4, 1, 0] of the status register if Status Register bit 3 =0. It will not affect the current state bits.
Data 5.4.2.1 She et DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or has completed. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. Note that the Data# Polling is valid only for the last word being programmed in the writebuffer-page during Write Buffer Programming.
D at a 5.4.2.2 S hee t DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Program Suspend or Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation). During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle.
Data 5.4.2.5 She et Reading Toggle Bits DQ6/DQ2 Refer to Figure 5.5 on page 39 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the previous value.
D at a 5.4.2.7 S hee t DQ1: Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a 1. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the EAC to standby (Read Mode) and the Status Register failed bits are cleared. See Write Buffer Programming on page 28 for more details. Table 5.
Data 5.5.1 She et Embedded Operation Error If an error occurs during an embedded operation (program, erase, blank check, or password unlock) the device (EAC) remains busy. The RY/BY# output remains Low, data polling status continues to be overlaid on all address locations, and the status register shows ready with valid status bits. The device remains busy until the error status is detected by the host system status monitoring and the error status is cleared.
D at a 5.5.2 S hee t Protection Error If an embedded algorithm attempts to change data within a protected area (program, or erase of a protected sector or OTP area) the device (EAC) goes busy for a period of 20 to 100 µs then returns to normal operation. During the busy period the RY/BY# output remains Low, data polling status continues to be overlaid on all address locations, and the status register shows not ready with invalid status bits (SR[7] = 0).
Data 5.5.3 She et Write Buffer Abort If an error occurs during a Write to Buffer command the device (EAC) remains busy. The RY/BY# output remains Low, data polling status continues to be overlaid on all address locations, and the status register shows ready with valid status bits. The device remains busy until the error status is detected by the host system status monitoring and the error status is cleared.
D at a 5.6 S hee t Embedded Algorithm Performance Table Table 5.4 Embedded Algorithm Characteristics (-40°C to +85°C) Parameter Typ (Note 2) Max (Note 3) Unit Sector Erase Time 128 kbyte 275 1100 ms Single Word Programming Time (Note 1) 125 400 µs 2-byte (Note 1) 125 750 32-byte (Note 1) 160 750 64-byte (Note 1) 175 750 128-byte (Note 1) 198 750 256-byte (Note 1) 239 750 512-byte 340 750 512-byte 1.
Data She et Table 5.5 Embedded Algorithm Characteristics (-40°C to +105°C) Parameter Sector Erase Time 128 kbyte Single Word Programming Time (Note 1) Typ (Note 2) Max (Note 3) Unit 275 1100 ms µs 125 400 2-byte (Note 1) 150 1050 32-byte (Note 1) 200 1050 64-byte (Note 1) 220 1050 128-byte (Note 1) 250 1050 256-byte (Note 1) 320 1050 512-byte 420 1050 512-byte 1.
D at a 5.6.1 S hee t Command State Transitions Table 5.6 Read Command State Transition Current State Command and Condition Read Software Reset / ASO Exit Status Register Read Enter Status Register Clear Unlock 1 Blank Check CFI Entry Address RA xh x555h x555h x555h (SA)555h (SA)55h Data RD xF0h x70h x71h xAAh x33h x98h Read Protect = False READ READ READSR (READ) READ READUL1 - (return) - - READ READSR - - CFI BLCK - - - Table 5.
Data She et Table 5.9 Erase Suspend State Command Transition Current State Command and Condition Read Software Reset / ASO Exit Status Register Read Enter Status Register Clear Unlock 1 Sector Erase Start Address RA xh x555h x555h x555h (SA)xh Data RD xF0h x70h x71h xAAh x30h - ESR ERSR (ESR) - - ESR (1) - SR(7) = 0 - ES ES ES ESSR (ES) ES ESUL1 SR(7) = 1 ESSR SER - (return) - - - - - Note: 1. State will automatically move to ES state by tESL. Table 5.
D at a S hee t Table 5.
Data She et Table 5.
D at a S hee t Table 5.
Data She et Table 5.
D at a S hee t Table 5.
Data She et Table 5.26 State Transition Definitions (Sheet 1 of 2) Current State Command Transition Definition BLCK Table 5.8 Blank Check CER Table 5.8 Chip Erase Start CFI Table 5.18 ID (Autoselect) CFISR Table 5.18 ID (Autoselect) - Status Register Read DYB Table 5.25 DYB ASO DYBEXT Table 5.25 DYB ASO - Command Exit DYBSET Table 5.25 DYB ASO - Set DYBSR Table 5.25 DYB ASO - Status Register Read ER Table 5.8 Erase Enter ERSR Table 5.
D at a S hee t Table 5.26 State Transition Definitions (Sheet 2 of 2) Current State 56 Command Transition Definition PPBPG1 Table 5.23 PPB - Program Request PPBSR Table 5.23 PPB - Status Register Read PPD Table 5.22 Password ASO - Data PPEXT Table 5.22 Password ASO - Command Exit PPPG Table 5.22 Password ASO - Program PPPG1 Table 5.22 Password ASO - Program Request PPSR Table 5.22 Password ASO - Status Register Read PS Table 5.16 Program Suspended PSR Table 5.
Data 6. She et Software Interface Reference 6.1 Command Summary Command Sequence (Note 1) Cycles Table 6.
D at a S hee t Command Sequence (Note 1) Cycles Table 6.
Data She et Command Sequence (Note 1) Cycles Table 6.
D at a 6.2 S hee t Device ID and Common Flash Interface (ID-CFI) ASO Map The Device ID portion of the ASO (word locations 0h to 0Fh) provides manufacturer ID, device ID, Sector Protection State, and basic feature set information for the device. ID-CFI Location 02h displays sector protection status for the sector selected by the sector address (SA) used in the ID-CFI enter command.
Data She et Table 6.
D at a S hee t Table 6.
Data She et Table 6.6 CFI Primary Vendor-Specific Extended Query (Sheet 1 of 2) Word Address Data (SA) + 0040h 0050h (SA) + 0041h 0052h (SA) + 0042h 0049h (SA) + 0043h 0031h (SA) + 0044h 0035h Description Query-unique ASCII string “PRI” Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 00b = Required 01b = Not Required Process Technology (Bits 5-2) 0000b = 0.23 µm Floating Gate 0001b = 0.17 µm Floating Gate (SA) + 0045h 001Ch 0010b = 0.
D at a S hee t Table 6.
Data She et Hardware Interface 7. Signal Descriptions 7.1 Address and Data Configuration Address and data are connected in parallel (ADP) via separate signal inputs and I/Os. 7.2 Input/Output Summary Table 7.1 I/O Summary Symbol 7.3 Type Description Hardware Reset. At VIL, causes the device to reset control logic to its standby state, ready for reading array data. RESET# Input CE# Input Chip Enable. At VIL, selects the device for data transfer with the host memory controller.
D at a 7.4 S hee t Ready/Busy# (RY/BY#) RY/BY# is a dedicated, open drain output pin that indicates whether an Embedded Algorithm, Power-On Reset (POR), or Hardware Reset is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in a command sequence, when VCC is above VCC minimum during POR, or after the falling edge of RESET#. Since RY/BY# is an open drain output, several RY/BY# pins can be tied together in parallel with a pull up resistor to VIO.
Data 8. She et Signal Protocols The following sections describe the host system interface signal behavior and timing for the 29GL-S family flash devices. 8.1 Interface States Table 8.1 describes the required value of each interface signal for each interface state. Table 8.
D at a 8.3 8.3.1 S hee t Power Conservation Modes Interface Standby Standby is the default, low power, state for the interface while the device is not selected by the host for data transfer (CE# = High). All inputs are ignored in this state and all outputs except RY/BY# are high impedance. RY/BY# is a direct output of the EAC, not controlled by the Host Interface. 8.3.
Data 8.4.2 She et Random (Asynchronous) Read When the host system interface selects the memory device by driving CE# Low, the device interface leaves the Standby state. If WE# is High when CE# goes Low, a random read access is started. The data output depends on the address map mode and the address provided at the time the read access is started. The data appears on DQ15-DQ0 when CE# is Low, OE# is Low, WE# remains High, address remains stable, and the asynchronous access times are satisfied.
D at a 8.5.2 S hee t Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on WE# will not initiate a write cycle. 8.5.3 Logical Inhibit Write cycles are inhibited by holding OE# at VIL, or CE# at VIH, or WE# at VIH. To initiate a write cycle, CE# and WE# must be Low (VIL) while OE# is High (VIH). 70 GL-S MirrorBit® Family IS29GL_128S_01GS_00_Rev.
Data 9. She et Electrical Specifications 9.1 Absolute Maximum Ratings Table 9.1 Absolute Maximum Ratings Storage Temperature Plastic Packages -65°C to +150°C Ambient Temperature with Power Applied -65°C to +125°C Voltage with Respect to Ground All pins other than RESET# (Note 1) -0.5V to (VIO + 0.5V) RESET# (Note 1) -0.5V to (VCC + 0.5V) Output Short Circuit Current (Note 2) 100 mA VCC -0.5V to +4.0V VIO -0.5V to +4.0V Notes: 1. Minimum DC voltage on input or I/O pins is -0.5V.
D at a S hee t Table 9.2 Power-Up/Power-Down Voltage and Timing Symbol Parameter Min Max Unit VCC VCC Power Supply 2.7 3.6 V VLKO VCC level below which re-initialization is required (Note 1) 2.25 2.5 V VRST VCC and VIO Low voltage needed to ensure initialization will occur (Note 1) 1.0 V tVCS VCC and VIO minimum to first access (Note 1) 300 µs tPD Duration of VCC VRST(min) (Note 1) 15 µs Note: 1. Not 100% tested. Figure 9.
Data 9.3.4 She et Input Signal Overshoot Figure 9.3 Maximum Negative Overshoot Waveform 20 ns 20 ns VIL max VIL min –2 .0 V 20 n s Figure 9.4 Maximum Positive Overshoot Waveform 20 ns VIO + 2.0 V VIH max VIH min 20 ns February 2015 IS29GL_128S_01GS_00_Rev.
D at a 9.4 S hee t DC Characteristics Table 9.3 DC Characteristics (-40°C to +85°C) Parameter Typ (Note 2) Max Unit VIN = VSS to VCC, VCC = VCC max +0.02 ±1.0 µA Description Test Conditions Min ILI Input Load Current ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max +0.02 ±1.
Data She et Table 9.4 DC Characteristics (-40°C to +105°C) Parameter Description Test Conditions Min Typ (Note 2) Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max +0.02 ±1.0 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max +0.02 ±1.
D at a 9.5 S hee t Capacitance Characteristics Table 9.5 Connector Capacitance for FBGA (LAA) Package Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 8 9 pF COUT Output Capacitance VOUT = 0 5 7 pF CIN2 Control Pin Capacitance VIN = 0 4 8 pF RY/BY# Output Capacitance VOUT = 0 3 4 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. Table 9.
Data She et 10. Timing Specifications 10.1 Key to Switching Waveforms Waveform Inputs Outputs Steady Changing from H to L Changing from L to H 10.2 Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High-Z) AC Test Conditions Figure 10.1 Test Setup Device Under Test CL Table 10.1 Test Specification All Speeds Units Output Load Capacitance, CL Parameter 30 pF Input Rise and Fall Times (Note 1) 1.5 ns 0.
D at a 10.3 S hee t Power-On Reset (POR) and Warm Reset Normal precautions must be taken for supply decoupling to stabilize the VCC and VIO power supplies. Each device in a system should have the VCC and VIO power supplies decoupled by a suitable capacitor close to the package connections (this capacitor is generally on the order of 0.1 µF). Table 10.
Data 10.3.2 She et Hardware (Warm) Reset During Hardware Reset (tRPH) the device will draw ICC5 current. When RESET# continues to be held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL, but not at VSS, the standby current is greater. If a Cold Reset has not been completed by the device when RESET# is asserted Low after tVCS, the Cold Reset# EA will be performed instead of the Warm RESET#, requiring tVCS time to complete. See Figure 10.4, Hardware Reset on page 79.
D at a 10.4 S hee t AC Characteristics 10.4.1 Asynchronous Read Operations Table 10.3 Read Operation VIO = VCC = 2.7V to 3.
Data She et Table 10.5 Read Operation VIO = VCC = 2.7V to 3.
D at a S hee t Figure 10.5 Back to Back Read (tACC) Operation Timing Diagram tACC tOH Amax-A0 tDF tCE tOH CE# tDF tOE tOH OE# DQ15-DQ0 Figure 10.6 Back to Back Read Operation (tRC)Timing Diagram tRC tACC tOH Amax-A0 tCE CE# tOE tOH tDF OE# DQ15-DQ0 Note: Back to Back operations, in which CE# remains Low between accesses, requires an address change to initiate the second access. Figure 10.
Data 10.4.2 She et Asynchronous Write Operations Table 10.7 Write Operations Parameter VIO = 2.7V to VCC Description VIO = 1.
D at a S hee t Figure 10.9 Back to Back (CE#VIL) Write Operation Timing Diagram tWC Amax-A0 tAS tAH tCS CE# OE# tWP tWPH WE# tDS tDH DQ15-DQ0 Figure 10.10 Write to Read (tACC) Operation Timing Diagram tAH tAS tSR_W tACC tOH Amax-A0 tOH tCS tDF CE# tOH tOEH tOE tDF OE# tWP WE# tDH tDS DQ15-DQ0 84 GL-S MirrorBit® Family IS29GL_128S_01GS_00_Rev.
Data She et Figure 10.11 Write to Read (tCE) Operation Timing Diagram tAH tAS tSR_W tACC tOH Amax-A0 tOH tCS tCH tCE tDF CE# tOH tOEH tOE tDF OE# tWP WE# tDH tDS DQ15-DQ0 Figure 10.12 Read to Write (CE# VIL) Operation Timing Diagram tAS tACC tOH tAH Amax-A0 tCE tCH CE# tGHWL tOH tOE tDF OE# tWP WE# tDS tDH DQ15-DQ0 February 2015 IS29GL_128S_01GS_00_Rev.
D at a S hee t Figure 10.13 Read to Write (CE# Toggle) Operation Timing Diagram tAS tACC tOH tAH Amax-A0 tOH tCE tDF tCS tCH CE# tGHWL tOH tOE tDF OE# tWP WE# tDH tDS DQ15-DQ0 Table 10.8 Erase/Program Operations Parameter VIO = 2.7V to VCC Description JEDEC Std tWHWH1 tWHWH1 tWHWH2 tWHWH2 VIO = 1.
Data She et Figure 10.14 Program Operation Timing Diagram Program Command Sequence (last two cycles) tAS tWC Addresses Read Status Data (last two cycles) 555h PA PA PA tAH CE# tCH OE# tWHWH1 tWP WE# tWPH tCS tDS tDH PD A0h Data Status DOUT tBUSY tRB RY/BY# Note: 1. PA = program address, PD = program data, DOUT is the true data at the program address. Figure 10.
D at a S hee t Figure 10.16 Data# Polling Timing Diagram (During Embedded Algorithms) tRC Addresses VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement True Valid Data Status Data Status Data True Valid Data High Z DQ6–DQ0 tBUSY RY/BY# Note: 1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 10.
Data 10.4.3 She et Alternate CE# Controlled Write Operations Table 10.9 Alternate CE# Controlled Write Operations Parameter VIO = 2.7V to VCC Description VIO = 1.
D at a S hee t Figure 10.20 (CE#) Write to Read Operation Timing Diagram tWC tAS tACC Amax-A0 tAH tCE tDF CE# tOEH tOE OE# tWS tWH WE# tDH tDS tOH DQ15-DQ0 90 GL-S MirrorBit® Family IS29GL_128S_01GS_00_Rev.
Data She et 11. Physical Interface 11.1 56-Pin TSOP 11.1.1 Connection Diagram Figure 11.
D at a 11.1.2 S hee t Physical Diagram Figure 11.2 56-Pin Thin Small Outline Package (TSOP), 14 x 20 mm PACKAGE SYMBOL MO-142 (B) EC MIN. NOM. MAX. 1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.) A --- --- 1.20 2 PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP). A1 0.05 --- 0.15 3 A2 0.95 1.00 1.05 b1 0.17 0.20 0.23 TO BE DETERMINED AT THE SEATING PLANE -C- .
Data 11.2 She et 64-Ball FBGA 11.2.1 Connection Diagram Figure 11.
D at a 11.2.2 S hee t Physical Diagram – LAE064 Figure 11.4 LAE064—64-ball Fortified Ball Grid Array (FBGA), 9 x 9 mm NOTES: PACKAGE LAE 064 JEDEC 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. N/A 2. ALL DIMENSIONS ARE IN MILLIMETERS. 9.00 mm x 9.00 mm PACKAGE 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010? EXCEPT AS NOTED). SYMBOL MIN NOM MAX NOTE A --- --- 1.40 A1 0.40 --- --- STANDOFF A2 0.60 --- --- BODY THICKNESS PROFILE HEIGHT D 9.00 BSC. BODY SIZE E 9.
Data 11.2.3 She et Physical Diagram – LAA064 NOTES: PACKAGE LAA 064 JEDEC 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. N/A 2. ALL DIMENSIONS ARE IN MILLIMETERS. 13.00 mm x 11.00 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.40 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). NOTE PROFILE HEIGHT A1 0.40 --- --- STANDOFF A2 0.60 --- --- BODY THICKNESS D 13.00 BSC. E 11.00 BSC. BODY SIZE 7.00 BSC. MATRIX FOOTPRINT E1 7.00 BSC.
D at a 11.3 S hee t 56-Ball FBGA 11.3.1 Connection Diagram Figure 11.
Data 11.3.2 She et Physical Diagram - VBU 056 A D D1 e 0.10 C (2X) 8 7 SE 7 6 5 E E1 4 3 e 2 1 9 H A1 CORNER INDEX MARK B TOP VIEW G F E D C B A A1 CORNER 6 SD 56 b 0.10 C 7 0.08 M C 0.15 M C A B (2X) BOTTOM VIEW 0.10 C A A1 SEATING PLANE C 0.08 C SIDE VIEW NOTES: PACKAGE VBU 056 JEDEC 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. N/A 2. ALL DIMENSIONS ARE IN MILLIMETERS. 9.00 mm x 7.00 mm NOM PACKAGE SYMBOL MIN NOM MAX A --- --- 1.
D at a S hee t 13. Ordering Information Valid Combinations Table 13.1 lists configurations planned to be available in volume. The table will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific combinations and to check on newly released combinations. Table 13.
Data She et Table 13.
D at a S hee t The ordering part number for the General Market device is formed by a valid combination of the following: IS29GL01GS 10 D H I 01 TR Packing Type TR = 13” Tape and Reel blank = Tray Model Number (VIO and VCC Range) 01 = VIO = VCC = 2.7 to 3.6V, highest address sector protected 02 = VIO = VCC = 2.7 to 3.6V, lowest address sector protected V1 = VIO = 1.65 to VCC, VCC = 2.7 to 3.6V, highest address sector protected V2 = VIO = 1.65 to VCC, VCC = 2.7 to 3.
