User`s guide

6-4
For example, in most link power nodes that use the Neuron 3120 Chip, the only fast
digital signal that needs to be routed across the PC board is the CLK2 line from the
Neuron Chip to the LPT-10 transceiver (CLK on transceiver pin 7, see figure 2.1). If a
two-layer PC board is being used, CLK2 can be routed to the transceiver pin with ground
guard traces straddling the clock trace on the component side of the board, and a wide
ground trace (or ground plane) covering the underside of the clock trace on the solder
side of the PC board. If a four-layer PC board is being used, the clock trace can be buried
in an inner layer and guarded on all four sides. The CLK2 trace from the Neuron Chip to
the LPT-10 transceiver should be as short as practical, and in all cases ≤ 2cm.
It may be possible to minimize C
leak,SIGNAL
by spacing the node's circuitry away
from any nearby metal using a plastic package or standoffs, and there may be some
mechanical configurations where there will never be earth ground near a link power
node, i.e., motion sensors that hang from ceilings. For most nodes, though, logic ground
guarding of fast digital signals will be required to meet "B" levels of EMC.
Since the Neuron 3150 Chip has an external memory interface bus, there are many more
traces in a Neuron 3150 Chip-based link power node that need to be guarded by logic
ground. In addition, the Vcc noise generated by the memory interface and external
ROM/RAM components requires more Vcc decoupling, and may require a four-layer PC
board to maintain an RF-quiet Vcc and logic ground.
If the link power node's application circuitry uses fast digital signals, the same EMC
design rules apply. Some link power nodes with fast circuitry such as DSP engines and
memory arrays, etc. may require extra RF attenuation between the LPT-10 transceiver
and the twisted pair network in order to meet level "A" or "B". This extra attenuation
can be provided by a common-mode ferrite choke in series with the NET_A and NET_B
lines near the network connector. A common-mode ferrite choke, such as muRata's
PLT1R53C, can provide an additional 10-15dB of attenuation over the 30-300MHz RF
band. Note that a common-mode choke must be used because of the differential DC
current (≤ 50mA) that the LPT-10 transceiver draws from the network to power the
node. Individual ferrite beads on the NET_A and NET_B lines can only be used if they
are large enough not to be saturated by this DC network current flowing into the node.
In summary, the following general trends apply for link power EMC:
• the faster the Neuron Chip clock speed (1.25MHz to 10MHz), the higher the level
of EMI;
• better Vcc decoupling quiets RF noise at the sources (the digital ICs), which lowers
EMI;
• the Neuron 3120 Chip will generate less EMI than the Neuron 3150 Chip since the
3120 has no external memory interface lines;
• a four-layer PC board will generate less EMI than a two-layer PC board since the
extra layers facilitate better Vcc decoupling and more effective logic ground
guarding;
• a two-layer link power node based on a 5MHz Neuron 3120 Chip should be able to
meet FCC/VDE level "B" EMC if good decoupling and ground guarding of the CLK2
line are used;
• a common-mode ferrite choke can be used to help meet EMC requirements for nodes
that have noisy application circuitry or special circuit requirements.