User`s guide

LONWORKS LPT-10 Transceiver User’s Guide 6-3
TWISTED
PAIR
NETWORK
LEAKAGE
CAPACITANCES
TO EARTH
GROUND
C leak,GND
C load
LPT-10
Vcc
NODE
LOGIC
GROUND
"FLOATING" NODE ON LINK POWER NETWORK
C decouple
C leak,SIGNAL
Vgate
NET_A
NET_B
Vcc
GND
Figure 6.1 Parasitic Leakage Capacitances to Earth Ground
The single most important technique for designing an EMI “quiet” floating node is to use
logic ground to guard any fast digital signal lines. Effective guarding of traces with
logic ground reduces C
leak,SIGNAL
significantly, which in turn reduces the level of
common-mode RF currents driven onto the network cable.
When a node is mounted near a piece of metal, especially metal that is earth grounded,
any leakage capacitance from fast signal lines to that external metal will provide a
path for RF currents to flow. When V
gate
is pulled down to logic ground, the voltage of
logic ground with respect to earth ground will increase slightly. When V
gate
pulls up
to Vcc, logic ground will be pushed down slightly with respect to earth ground. As
C
leak,SIGNAL
increases, a larger current flows during V
gate
transitions, and more
common-mode RF current couples to the network twisted pair. This common-mode RF
current can generate EMI in the 30-300MHz frequency band in excess of “B” levels even
when C
leak,SIGNAL
from a clock line to earth ground is less than 1pF, so guarding of
clock lines is essential for meeting Level “B” requirements.
From this discussion, it is apparent that minimizing C
leak,SIGNAL
is very important.
By using 0.1µF or 0.01µF decoupling capacitors at each digital IC power pin, Vcc and
logic ground noise can be reduced. Logic ground can then be used as a ground shield for
other noisy digital signals and clock lines.