User`s guide

2-8
The +5VDC Vcc trace and GROUND trace are shown leading away from the
transceiver into the general board area for the Neuron Chip and application circuit.
The Vcc and GROUND should be routed directly off the C2 capacitor to the node's
circuitry as shown. The ground guarding around the network connector should not be
used as a source of ground for the digital circuitry. C3 is a small 0.1µF decoupling
capacitor that should be placed near C2 to help keep digital switching noise from
returning to the LPT-10 transceiver's Vcc input (pin 5).
The CLK input to the LPT-10 transceiver (pin 7) needs to be guarded by ground traces to
minimize clock noise, and to help keep EMI levels low (see Chapter 6). In general, the
Neuron 3120 or 3150 Chip should be placed close enough to the LPT-10 transceiver and
oriented correctly so that the CLK trace from the Neuron Chip to the transceiver is no
longer than 2cm. At the same time, the Neuron Chip and any other fast digital circuitry
should be kept away from the network connector and NET_A/NET_B pins (pins 1 and 2)
on the transceiver. If noisy digital circuity is located too close to the network connector or
wires, RF noise may couple onto the network cable and cause EMI problems. With these
constraints in mind, it is apparent that the best place to locate the Neuron Chip is in the
lower right corner of figure 2.3, with an orientation that places the Neuron Chip’s CLK2
line closest to the transceiver's CLK input pin. This position and orientation work well
for both the Neuron 3120 and 3150 Chips, since the CP lines are oriented near the lower
portion of the LPT-10 transceiver for the rest of the interconnections.
Choosing the Inductor and Capacitors for the LPT-10
Switching Power Supply
Parts that are chosen for L1, C1 and C2 must meet several key specifications to ensure
that the switching power supply conversion performed by the LPT-10 transceiver stays
within specified limits. As long as these key specifications are met, the designer of a
link power node is free to choose parts that have other specifications that best match
the application. These specifications allow up to 100mA of sustained peak current to be
drawn by the application, including Neuron Chip. Component selection for low-current
applications is discussed in the next section.
Suitable parts for inductor L1 are listed in table 2.4. L1 has the following key
specifications that must be met over the node's operating temperature range: L = 1mH
±10%, I
sat
≥ 200mA, DCR ≤ 4Ω where I
sat
is defined as the current required to decrease
the inductance to 80% of the low-current inductance. For low-current applications,
inductors with saturation currents (I
sat
) down to 80mA can be used, but the peak
application current should not exceed half of the I
sat
rating.