User`s guide

LONWORKS LPT-10 Transceiver User’s Guide 2-5
Clock Select
The CLKSEL0 and TXD/CLKSEL1 pins are used to indicate the frequency of the input
clock (CLK). CLKSEL0 may be tied directly to Vcc or GND. The TXD/CLKSEL1 must
be tied through a pull-up or pull-down 47kΩ resistor. VCS0 and VCS1 are shown in
figure 2.1. The clock select options are shown in table 2.2.
Table 2.2 Clock Select Options
VCS1 VCS0 CLK Frequency
GND GND 10MHz
GND 5V 5MHz
5V GND 2.5MHz
5V 5V 1.25MHz
Neuron Chip Communications Port (CP) Lines
The LPT-10 transceiver transmits and receives LonTalk network packets via the Neuron
Chip's direct, single-ended mode over CP0-3. CP0 is the data input to the Neuron Chip
and is connected to the LPT-10 transceiver's RXD pin. CP1 is the data output from the
Neuron Chip and is connected to the TXD/CLKSEL1 pin; this pin also serves as one of
the input clock select pins. CP2 is the transmit enable output from the Neuron Chip and
is connected to the TXEN pin. CP3 is the ~sleep (~power-down) output from the Neuron
Chip and is connected to the ~SLEEP pin. These connections are summarized in table
2.3.
Table 2.3 Neuron Chip CP Line Connections
Neuron Chip Pin Neuron Chip Function LPT-10 Pin
CP0 Data input RXD
CP1 Data output TXD/CLKSEL1
CP2 Transmit enable output TXEN
CP3 ~Sleep(~power-down) output ~SLEEP
PC Board Layout Guidelines
The recommended PC board layout for the LPT-10 transceiver and its external
components is shown in figure 2.3.
Variations on this suggested PC board layout are possible as long as the general
principles of grounding, shielding, guarding and spacing are employed. For example,
the LPT-10 transceiver pins can be formed into a right angle before the transceiver is