User`s guide

2-4
Reset
Follow the recommendations of the Neuron 3120 Chip and Neuron 3150 Chip Data Book
with regard to reset (references [2] and [3]). An external low voltage indicator (LVI)
suitable for use with a ±10% power supply must be used as shown in figure 2.1. The LVI
must have an open-collector or open-drain drive characteristic to be compatible with
the Neuron Chip's bidirectional ~RESET line. Figure 2.1 also shows two 100pF
capacitors decoupling the ~RESET line of the Neuron Chip. These capacitors improve
ESD immunity for the Neuron Chip, and are required by the LPT-10 for proper reset
timing.
In applications with significant leakage capacitance (>5pF) from the node to external
ground, the reset circuit of figure 2.2 may be used to improve ESD or similiar noise
immunity.
~RESET
~RESET
100pF
100pF
LVI
+5V
1000pF
1000pF
DS1233Z-10
LPT-10
LINK POWER
TRANSCEIVER
~RESET
10kΩ
Figure 2.2 LPT-10 Transceiver -- Alternate Reset Circuit
Network Connection
The network connection (NET_A and NET_B) is polarity insensitive, and therefore
either of the two twisted pair wires can be connected to either of the two NET pins.
Details on network wiring are discussed in Chapter 5.
Transient protection may be required to protect the LPT-10 transceiver against surge
voltages resulting from transient switching and lightning strikes. Details on surge
protection are discussed in Chapter 6.
Clock Input
The LPT-10 transceiver receives its clock input from the Neuron Chip via the CMOS
input CLK pin. This pin is driven by the CLK2 output of the Neuron Chip, whether the
Neuron Chip's oscillator or an external clock oscillator is used. Clock traces should be
kept short (≤ 2cm) to minimize noise coupling.
The LPT-10 transceiver can operate at 10, 5, 2.5, or 1.25MHz. The operating frequency is
selected via the CLKSEL0 and TXD/CLKSEL1 pins.