User`s guide

2-2
LPT-10 Pinout
The pinout of the LPT-10 transceiver is shown in table 2.1. The interconnection between
the LPT-10 and a Neuron Chip is shown in the block diagram in figure 2.1. See figure
3.1 for the physical location of pin 1.
Table 2.1 LPT-10 Transceiver Pinout
Name Pin# Function
NET_A 1 Connection to TP network, polarity insensitive
NET_B 2 Connection to TP network, polarity insensitive
V+ 3 Power supply input voltage (≈ 35VDC)
INDUCTOR 4 Power supply inductor connection
V
cc
5 +5VDC power for transceiver operation
GND 6 Power supply ground
CLK 7 Transceiver clock input from Neuron Chip
CLKSEL0 8 Input clock speed select
TXD/CLKSEL1 9 Neuron Chip CP1 and input clock speed select
RXD 10 Neuron Chip CP0
TXEN 11 Neuron Chip CP2
~RESET 12 ~RESET
~SLEEP 13 Neuron Chip CP3 (powers down the transceiver)
WAKEUP_CAP 14 Wake-up timer
WAKEUP_OUT 15 Wake-up output to Neuron Chip I/O line
RX_ACTIVE 16 Repeater output