L O N W ORKS ® LPT-10 Link Power Transceiver User’s Guide Version 2.
States and other countries. LonLink and L ONMARK are trademarks of Echelon Corporation. Other names may be trademarks of their respective companies. Other brand and product names are trademarks or registered trademarks of their respective holders.
Contents 1 Introduction Applications Audience Content Related Documentation 2 Electrical Interface LPT-10 Pinout Network Connection Reset Clock Input Clock Select Neuron Chip Communications Port (CP) Lines PC Board Layout Guidelines Choosing the Inductor and Capacitors for the LPT-10 Switching Power Supply Alternative Inductor and Capacitor Selection for Low-Current Applications Wake-Up Timer Physical Layer Repeater 3 Mechanical Considerations Mechanical Footprint 4 Power Output Transceiver Output P
6 Design Issues EMI Design Issues Designing Systems for EMC (Electromagnetic Compatibility) ESD Design Issues Designing Systems for ESD Immunity Surge Design Issues Designing Systems for Surge Immunity Vibration and Mechanical Shock Issues IEC-801 Testing 7 Programming Considerations Application Program Development and Export 8 References Reference Documentation iv 6-1 6-2 6-2 6-5 6-5 6-6 6-6 6-7 6-7 7-1 7-2 8-1 8-2 Echelon
1 Introduction The LPT-10 Link Power Twisted Pair Transceiver provides a simple, cost effective method of adding a network-powered LONW ORKS transceiver to any Neuron® Chip-based machine controller, process controller, fire and security device, or general purpose controller.
The LPT-10 transceiver includes an integral switching power supply that can furnish +5VDC at up to 100mA. The LPT-10 transceiver derives its power directly from the switching power supply, providing up to 100mA of current for a Neuron Chip, application electronics, sensors, actuators, and displays. The high current capability of the LPT10 transceiver eliminates the need for local power supplies at each node, resulting in equipment and labor cost savings.
Applications A conventional control system using bus topology wiring (such as RS-485) consists of a network of sensors and control outputs that are interconnected using a shielded twisted wire pair. In accordance with EIA RS-485 guidelines, all of the devices must be wired in a bus topology to limit electrical reflections and ensure reliable communications. There is a high cost associated with installing and maintaining the cable plant that links together the many elements of an RS-485-based control system.
LPT-10 Node FTT-10 Node 48VDC Power Supply To additional LPT-10 or FTT-10 nodes LPI-10 Interface LPT-10 Node FTT-10 Node LPT-10 Node Figure 1.1 Free Topology Link Power System LPT-10 Link Power Transceivers located along the twisted wire pair include integral switching power supplies. These supplies regulate the power on the twisted pair to +5VDC at currents up to 100mA for use by the Neuron Chip and the various sensors, actuators, and displays.
accommodated with minimal, if any, rewiring. This capability ensures that link power technology can be adapted to both old and new projects, widening the potential market for link power-based products. Finally, free topology permits link power systems to be expanded in the future by simply tapping into the existing wiring where it is most convenient to do so. This reduces the time and expense of system expansion, and from the customer's perspective, keeps down the life cycle cost of the link power network.
System expansion is simplified in another important way, too. Each link power transceiver incorporates a repeater function. If a link power system grows beyond the maximum number of transceivers or total wire distance, then additional link power systems can be added by interconnecting transceivers using the repeater function (figure 1.3). The repeaters will transfer LonTalk® data between the two systems, doubling the number of transceivers as well as the length of wire over which they communicate.
Many link power applications, especially those utilizing battery-backed power supplies, will require that power consumption be minimized during normal operation. To accommodate these applications, the link power transceiver incorporates power management functions to reduce power consumption.
L O N W ORKS FTT-10 Free Topology Transceiver User's Guide (078-0114-01) L O N W ORKS Product Databook L O N W ORKS Custom Node Development (005-0024-01) 1-8
2 Electrical Interface The LPT-10 Link Power Transceiver’s 16 pins provide a polarity insensitive connection to the twisted pair network, an interface to the Neuron Chip communications port, a switching power supply, and a wakeup timer to awaken the Neuron Chip from sleep mode on a periodic basis.
LPT-10 Pinout The pinout of the LPT-10 transceiver is shown in table 2.1. The interconnection between the LPT-10 and a Neuron Chip is shown in the block diagram in figure 2.1. See figure 3.1 for the physical location of pin 1. Table 2.
NET_A TO NETWORK NET_B V+ L1 INDUCTOR C1 Vcc GND CLOCK CIRCUIT +5V C2 C3 GND CLK VCS0 VCS1 GROUND GUARD CLKSEL0 47k CLK2 CLK1 TXD/CLKSEL1 CP1 RXD CP0 +5V TXEN CP2 100pF ~RESET ~RESET 100pF ~SLEEP CP3 WAKEUP_CAP Cwu (optional) IO0 - IO10 WAKEUP_OUT RX_ACTIVE LPT-10 LINK POWER TRANSCEIVER +5V LVI MC33164 TO APPLICATION ELECTRONICS NEURON 3120 OR 3150 CHIP Figure 2.
Reset Follow the recommendations of the Neuron 3120 Chip and Neuron 3150 Chip Data Book with regard to reset (references [2] and [3]). An external low voltage indicator (LVI) suitable for use with a ±10% power supply must be used as shown in figure 2.1. The LVI must have an open-collector or open-drain drive characteristic to be compatible with the Neuron Chip's bidirectional ~RESET line. Figure 2.1 also shows two 100pF capacitors decoupling the ~RESET line of the Neuron Chip.
Clock Select The CLKSEL0 and TXD/CLKSEL1 pins are used to indicate the frequency of the input clock (CLK). CLKSEL0 may be tied directly to Vcc or GND. The TXD/CLKSEL1 must be tied through a pull-up or pull-down 47kΩ resistor. VCS0 and VCS1 are shown in figure 2.1. The clock select options are shown in table 2.2. Table 2.2 Clock Select Options VCS1 VCS0 CLK Frequency GND GND 10MHz GND 5V 5MHz 5V GND 2.5MHz 5V 5V 1.
soldered onto the PC board. In this case, the layout in figure 2.3 would be modified to accommodate horizontal (90°) mounting of the transceiver. If the transceiver is bent to the left in figure 2.3, then C1 should be moved up and to the right, above L1. L1 and C2 can shift down slightly to minimize the trace lengths for L1, C1 and C2 in this variation on the original layout.
(generally the solder side of the board) should contain as much ground plane as possible. The switching power supply circuit in the LPT-10 transceiver uses the external components L1, C1 and C2 as part of its switching regulator. Because moderate currents are switched at approximately 150kHz, it is very important that L1, C1 and C2 are placed close to the LPT-10 transceiver and oriented as shown in the figure.
The +5VDC Vcc trace and GROUND trace are shown leading away from the transceiver into the general board area for the Neuron Chip and application circuit. The Vcc and GROUND should be routed directly off the C2 capacitor to the node's circuitry as shown. The ground guarding around the network connector should not be used as a source of ground for the digital circuitry. C3 is a small 0.
Table 2.4 Example L1 Inductor Selections (1mH) Manufacturer (Series) Part Number Temperature Range Application Taiyo-Yuden (LHL08) LHL08-102J -25°C to +85°C * General Stetco (09P) 09P-102J -25°C to +85°C General TDK (TSL) TSL0807-102KR23 -20°C to +80°C General Caddell-Burns (0780) 0780-37 -55°C to +105°C Wide Temp. * Note: Echelon has tested the Taiyo-Yuden part from -40°C to +85°C. Suitable parts for the V+ input capacitor C1 are listed in table 2.5.
are commonly used in switching power supply circuits. ESR generally decreases with higher DC working voltage rating, so C2 will usually be a 50V or 63V capacitor to achieve the required ESR specifications even though C2 is connected to Vcc = 5V. Table 2.6 Example C2 Capacitor Selections (22µF, ≥10V, Low ESR) Manufacturer (Series) Part Number Temperature Range Application Panasonic (HFZ) ECA1JFZ220 -55°C to +105°C 20,000 hr.
WAKEUP_OUT pin will be triggered with a period from 1 to 100 seconds, respectively, with a tolerance of 20% of the period. The tolerance for the capacitor must be added to this tolerance to obtain the overall tolerance of the output period. The WAKEUP_OUT pin must be pulled high either with the Neuron Chip’s internal pullup or with an external resistor. If the wake-up timer is not used, the WAKEUP_CAP pin must be grounded.
Figure 2.5 Two-Way Repeater Schematic C1 L1 C3 5.0 MHz Osc INDUCTOR GND VCC V+ D Q F/F ~Q CLK RX_ACTIVE RXD TXEN TXD/CLKSEL1 NET_B WAKEUP_OUT WAKEUP_CAP CLKSEL0 ~RESET ~SLEEP NC Rr NC LVI +5V See Note 1 C15 Rr C13 C14 GND CLK RX_ACTIVE TXEN RXD T2 T1 NET_B NET_A TXD/CLKSEL1 CLKSEL0 ~RESET VCC FTT-10 D14B D13A D14A D13B +5V D12A D12B D11B D11A 4. Omit C18, C28, C38, and spark gaps if the node is floating. 3.
+5V RxD0 RxD1 RxD2 RxD3 LPT-10 ~SLEEP See Note 5 NET_A To/From Network Segment 1 Rr LVI NC RxA0 RxA1 RxA2 RxA3 ~RESET WAKEUP_OUT WAKEUP_CAP See Note 5 NET_B CLKSEL0 TXD/CLKSEL1 TxD/CS1 TxEn +5V TXEN RxD0 RxA0 RXD V+ RX_ACTIVE VCC Clk CLK See Note 1 INDUCTOR L1 GND D Q F/F ~Q C2 C1 NC +5V See Notes 2 and 3 FTT-10 C14 C13 VCC ~Reset 5.
+5V C24 C23 FTT-10 VCC See Notes 2 and 3 NET_A D21B D21A C21 + To/From Network Segment 3 Rr ~RESET ~Reset C25 NET_B D22A CLKSEL0 TxD/CS1 TxEn RxD2 RxA2 C22 + TXD/CLKSEL1 D22B +5V TXEN D23B RXD D24B C28 T1 Clk CLK GND T2 D23A (spark gaps) RX_ACTIVE D24A See Note 4 +5V ~Reset C34 C33 See Notes 2 and 3 FTT-10 VCC NET_A D31B D31A C31 + To/From Network Segment 4 Rr ~RESET C35 D32A CLKSEL0 TxD/CS1 TxEn RxD3 RxA3 C32 + NET_B TXD/CLKSEL1 D32B +5V TXEN RXD D33B D34B C38
3 Mechanical Considerations This chapter discusses the mechanical footprint and connectors of the LPT-10 Link Power Transceiver. Details of mounting the transceiver to an application electronics board containing a Neuron Chip are provided.
Mechanical Footprint The LPT-10 transceiver mechanical dimensions are shown in table 3.1, and the footprint and connector are shown in figure 3.1. The LPT-10 transceiver is generally mounted to the application board as a through-hole, soldered component. Decisions about component placement on the application electronics board must also consider electromagnetic interference (EMI) and electrostatic discharge (ESD) issues as discussed in Chapter 6 of this document. Figure 3.
31.50mm (1.24") max 8mm (0.315") max LPT-10 50040-01 ® 19.80mm (0.78") max 7.00mm ±0.5 (0.276" ±0.02) Pin 1 0.27mm (0.011") 1.8mm ±0.3 (0.071" ±0.012) Front View Figure 3.1 0.5mm (0.
4 Power Output This section describes the power supply portion of the LPT-10 Link Power Transceiver, and provides suggestions for using the 5V output current.
Transceiver Output Power The LPT-10 transceiver power supply circuit performs a number of key functions: • draws DC power from the twisted pair network without interfering with communications with other nodes; • regulates the output voltage (Vcc) to +5VDC ±10% with a sustained peak current of 100mA; • limits Vcc output current to prevent a node with a Vcc short circuit from reducing the network voltage; • uses an undervoltage shutdown circuit to prevent the transceiver from attempting to start up whe
IR LED driver's power supply may need to be isolated from Vcc with an L-C filter. Typical R-C and L-C filters for isolating loads are shown in figure 4.1 NET_A TO NETWORK NET_B V+ L1 INDUCTOR C1 +5V Vcc GND TO GENERAL CIRCUITRY C3 C2 Ro CLK Co1 TO SENSITIVE LOW-POWER ANALOG CIRCUITS CLKSEL0 Lo Co2 TO HIGHER-POWER RESONANT LOADS LPT-10 Figure 4.1 Post-Filtering of Vcc Use the following guidelines to design the resistor and capacitor values for the R-C filter: 1.
1. Choose an LC product that sets the filter cutoff frequency at least a decade below the frequency of the resonant current demand (fd) in the load. That is, choose LoCo2 ≥ 100/(4π2fd 2 ); 2. L must be large enough to keep the "effective capacitance" of Co2 as seen by the LPT-10 transceiver to less than 5% of the transceiver’s 22µF output capacitor C2. This can be accomplished by ensuring that Lo ≥ 1mH(Co2/1µF); 3.
5 Network Cabling and System Performance This chapter provides information about cabling and network connections for the LPT-10 Link Power Transceiver. This information includes a discussion of wire characteristics and power distribution issues.
Network Overview The link power system is designed to support free topology wiring, and will accommodate bus, star, loop, or any combination of these topologies. LPT-10 transceivers can be located at any point along the network wiring, as can the LPI-10 module and its associated power supply. This capability simplifies system installation and makes it easy to add nodes should the system need to be expanded. Figures 5.1 through 5.5 present five different network topologies. Supply/ Interface Figure 5.
Supply/ Interface Figure 5.4 Loop Topology Supply/ Interface Figure 5.5 Combination Loop/Bus Topology In the event that the limits on the number of transceivers or total wire distance are exceeded, then a link power physical layer repeater (figure 5.5) can be added to interconnect two link power systems and double the overall system capability (see Chapter 2). Echelon's media routers can also be used to interconnect the link power system with any other LON W ORKS channel.
System Performance and Cable Selection Link power performance has system, transmission, and power specifications which are outlined on the following pages. Each of the specifications should be met to ensure proper operation. The system designer may choose a variety of cables, depending on cost, availability and performance. Performance as outlined in the transmission and power specifications varies with cable type.
System Specifications • Up to 128 LPT-10 transceivers or 64 FTT-10 transceivers are allowed per network segment. • Both types of transceivers may be used on a given segment, provided that the following constraint is met: (1 x number of LPT-10 transceivers) + (2 x number of FTT-10 transceivers) ≤ 128 • The average temperature of the wire must not exceed +55°C, although individual segments of wire may be as hot as +85°C. • The sum of the application current of all the nodes in a segment must not exceed 3.
Transmission Specifications Table 5.2 Doubly-Terminated Bus Topology Specifications Maximum bus length Maximum stub length Belden 85102 2200 3 Belden 8471 2200 3 Level 4/22AWG 1150 3 JY (St) Y 2x2x0.8 750 3 Table 5.3 Units meters Free Topology Specifications Maximum node-to-node distance Maximum total wire length with 10, 5 or 2.5MHz input clocks Maximum total wire length with 1.
Power Specifications, Simplified Form A link power network allows for multiple branches, e.g., a star topology. A branch is defined as any length of twisted pair cable that extends from the LPI-10 module. Loop topologies can be formed by joining the ends of branches. Whereas system and transmission distance specifications involve the entire network, power specifications apply to individual branches. The closer the nodes on a branch are to the LPI-10 module, the more nodes that can be on that branch.
Table 5.4 Simplified Power Specifications Using JY (St) Y 2x2x0.8 Wire 320 meter branch length, Evenly distributed loading along a bus application current: 25 mA 50 mA 100 mA 320 meter branch length, Lumped loading or otherwise distributed application current: 25 mA 50 mA 100 mA 160 meter branch length, Lumped loading or otherwise distributed application current: 25 mA 50 mA 100 mA Nominal Worst Case Units 128 64 32 96 48 24 nodes 64 32 16 48 24 12 nodes 128 64 32 96 48 24 nodes Table 5.
Power Specifications for Extended Performance Although more complex, this alternative power specification allows for extended power performance. In addition, it features a separate derating for the average wire temperature. I is the average application current of a node. The distance of an LPT-10 transceiver from the LPI-10 module is the node distance, d.
In the following example, there are only two branches to check. Assume wire type is JY (St) Y 2x2x0.8 and average wire temperature is 25°C. Thus, α = 1. 2 nodes 100mA 5 nodes 100mA 50m LPI-10 50m 2 nodes 100mA 50m 20m 80m 5 nodes 100mA 50m 2 nodes 100mA 20m 3 nodes 100mA 2 nodes 100mA In the upper branch, (2*0.1A)(50m) + (5*0.1A)(100m) + (2*0.1A)(150m) = 90 Amp*meters ≤ K*α*β = (530 Amp*meters)(1)(81%) = 430 Amp*meters In the lower branch, (5*0.1A)(20m) + (2*0.1A)(100m) + (3*0.1A)(150m) + (2*0.
Example network 1 below illustrates the simplification process in three steps. Distances are drawn in relative proportion. The numbers represent +5V application currents, with 5x25 indicating 5 nodes of 25mA each at the same location. Use the equivalent power network from Step Three when applying the extended power performance specification. Example 1.
Here is a second example which illustrates the benefits of the extended performance specification and the importance of the sub-branching simplification procedure. Without simplifying the network, the sample topology fails to meet the power specification. However, the equivalent power network, which ignores the lengths of all but one of the sub-branches, meets the worst case extended performance power specification and is therefore an allowable topology.
Cable Termination A Link Power network segment requires termination for proper data transmission performance. A total termination impedance of approximately 52Ω is required. Free Topology Segment In a free topology segment, only one termination is required and may be placed anywhere on the free topology segment. The LPI-10 Link Power Interface, with jumper at "1 CPLR" setting, provides this termination.
6 Design Issues This chapter looks at design issues, and includes discussions of Electromagnetic Interference (EMI), Electrostatic Discharge (ESD), and Surge for the LPT-10 Link Power Transceiver.
EMI Design Issues The high-speed digital signals associated with microcontroller designs can generate unintentional Electromagnetic Interference (EMI). High-speed voltage transitions generate RF currents that can cause radiation from a product if a length of wire or piece of metal can serve as an antenna. Products that use the LPT-10 transceivers together with a Neuron Chip will generally need to demonstrate compliance with EMI limits established by various regulatory agencies.
"FLOATING" NODE ON LINK POWER NETWORK LPT-10 Vcc Vcc Vgate TWISTED PAIR NETWORK C decouple NET_A C load NET_B NODE LOGIC GROUND GND C leak,GND C leak,SIGNAL LEAKAGE CAPACITANCES TO EARTH GROUND Figure 6.1 Parasitic Leakage Capacitances to Earth Ground The single most important technique for designing an EMI “quiet” floating node is to use logic ground to guard any fast digital signal lines.
For example, in most link power nodes that use the Neuron 3120 Chip, the only fast digital signal that needs to be routed across the PC board is the CLK2 line from the Neuron Chip to the LPT-10 transceiver (CLK on transceiver pin 7, see figure 2.1).
Note that it may be possible to design a two-layer 10MHz Neuron 3150 Chip-based link power node that will pass level "B" in some applications, depending on the mechanical configuration. Early testing of prototype circuits at an outdoor EMI range should be used to determine the effectiveness of these EMC techniques in a particular application. ESD Design Issues Electrostatic Discharge (ESD) is encountered frequently in industrial and commercial use of electronic systems10.
ground (Cleak,GND) should be held below about 10-20pF to mitigate damage from network ESD hits. Surge Design Issues Surge voltages encountered in industrial and residential environments as a result of nearby switching transients and lightning can cause disturbances or failures to electronic communications systems. Transient voltages and currents can couple capacitively or magnetically to the twisted pair wiring of the link power system.
TVS devices used with LPT-10 transceivers must meet the following requirements: • bi-directional protection; • rated at 400W minimum peak power (10/1000µs waveform) rating; • working peak reverse voltage rating Vrwm ≥ 42.4V (-40 to +85°C); Vrwm should be as low as possible over the temperature range but not less than 42.4V.
Table 6.2 IEC 801 Test Descriptions IEC 801 Test 801-2 801-3 801-4 801-5 Description ESD Radiated Susceptibility Burst Surge Level Level 4 Level 2 Level 4 Level 1 (0.5kV) Level 2 (1.0kV)* Level 3 (2.0kV)* * Level 2 or 3 surge immunity is only available with revision C03 or later LPT-10 transceiver, and requires external TVS protection. IEC 801-2 ESD testing is performed on a metal test table using an ESD transient generator13.
7 Programming Considerations This section explains how to configure the LonBuilder Developer’s Workbench to communicate with LPT-10 nodes. It also covers considerations relating to channel definition.
Application Program Development and Export Application programs are initially developed, tested, and debugged using the LonBuilder Developer’s Workbench. See the LonBuilder User’s Guide for detailed instructions on developing and testing applications. The LonBuilder SMX Adapter with attached FTM-10 Modular Transceiver can be used with both the LPT-10 and FTT10 transceivers. The parameters for the FTT/link power channel definition are shown in table 7.2.
• Ensure that channel A of the router is connected to the backplane channel. For level 1 and 2 routers, a backplane transceiver must be installed in the router P2 channel A transceiver expansion connector. For level 3 routers, JP1 must be in the "B" position; • Mount an FTM-10 Modular Transceiver on a LonBuilder SMX Adapter; • Mount the LonBuilder SMX Adapter on the router P3 channel B transceiver expansion connector.
Table 7.2. Standard LPT-10 and FTT-10 Channel Definition for both Bus and Free Topologies Variable FT-10 Standard Transceiver Type Comm Mode Single-ended (see note 3) Comm Rate 78.13kbps Min Clock Rate 5MHz Num Priorities 4 Osc Accuracy 200ppm Osc Wakeup 0µsec Avg Packet Size 15 bytes Collision Detect No CD terminate after preamble No CD through packet end No Bit Sync Threshold 4.0 bits Rcv Start Delay 9.0 bits (see note 1) Rcv End Delay 0.0 bits Indeterm Time 24.
8 References This section provides a list of the reference material used in the preparation of this manual.
Reference Documentation [1] L O N W ORKS LPI-10 Link Power Interface Module User's Guide, Echelon Corporation, version 1.1 or later. [2] Motorola MC143150 Neuron Chip data book. [3] Toshiba TMPN3150 Neuron Chip data book. [4] L O N W ORKS Custom Node Development engineering bulletin, Echelon Corporation, 1992. [5] L O N W ORKS FTT-10 Free Topology Transceiver User's Guide, Echelon Corporation, version 1.1 or later. [6] 47CFR15, Subpart B (Unintentional Radiators), U.S.
