User`s guide

B-2 Appendix
B
FTT-10A Transceiver-based Node Checklist
FTT-10A Transceiver and Neuron Chip Connections
Item Check When
Completed
Description
1 Transceiver pins connected as shown in table 2.1.
2 Environmental and electrical specifications shown in table
2.2.
3 CLK2 from Neuron Chip connected via trace ≤2cm (0.8").
4 The recommended number and placement of 0.1µF bypass
capacitors are near the Neuron Chip. See the Neuron Chip
Data Book from Toshiba or Motorola.
5 The Neuron Chip and transceiver input clock frequency is
≥5MHz and accurate to at least ± 200 ppm.
6 CP2 and CP3 from the Neuron Chip are not connected to
the transceiver.
7 CP4 from the Neuron Chip is connected to VCC
8 The transceiver ground pin is connected to node ground,
with low-impedance traces, using a star pattern to a central
ground point.
9 The Neuron Chip and transceiver are placed adjacent to one
another on the same printed circuit board.
10 If required, a Low Voltage Interrupt (LVI) circuit with open
collector output (such as the Motorola MC33064) is used to
supply a reset signal to the Neuron Chip.
11 CLK2 guarded by ground traces.
12 Spark gaps, clamping diodes, and 1000 pF 2kV snubbing
capacitors used if air-discharge ESD requirements are
applicable.