User`s guide

5-4 Design

Issues

and may require a four-layer PCB to maintain an RF-quiet Vcc and logic

ground.

Some FTT-10A nodes with fast digital circuitry, such as DSP engines and

memory arrays, may require extra RF attenuation between the FTT-10A

transceiver and the twisted pair network in order to meet FCC/CISPR level "A"

or "B". This extra attenuation can be provided by a ferrite bead (muRata

BLM11A601 or equal) in series with each network line adjacent to the network

connector. Each of these ferrite beads must have an inductance of no more than

30µH. Alternately, a common mode choke (muRata PLT1R53C or equal) could be

used in place of the two ferrite beads.

Some amount of filtering may also be required on an FTT-10A node's power

supply input, depending on the level of noise generated by the application

circuitry. This is best accomplished by placing ferrite chokes in series with the

power input traces adjacent to the power connector. A typical power supply circuit

illustrating the placement of these ferrite chokes is shown in figure 5.2.

3-Terminal

Volta

e Re

ulator

OUT

GND

+5V

OUTPUT

Power

Connector

Input

L3, L4 Suppliers & Part Numbers:

Associated Components WB2-30T

Fair Rite 294366631

Figure 5.2 Illustration of Power Supply Input Filtering Using Ferrite Chokes

In summary, the following general rules apply:

• the faster the Neuron Chip clock speed, the higher the level of EMI;

• better Vcc decoupling quiets RF noise at the sources (the digital ICs), which

lowers EMI;

• the Neuron 3120 Chip will generate less EMI than the Neuron 3150 Chip since

the Neuron 3120 Chip has no external memory interface lines;

• a four-layer PCB will generate less EMI than a two-layer PCB since the extra

layers facilitate better Vcc decoupling and more effective logic ground

guarding;

• a two-layer FTT-10A node should be able to meet FCC/CISPR level "B" EMC

if good decoupling and ground guarding are used;