User`s guide

LONWORKS FTT-10A Transceiver User’s Guide 5-3
Twisted
Pair
Network
Leakage
Capacitances to
Earth Ground
C leak,GND
C load
FTT-10A
Vcc
Node
Logic
Ground
"Floating" Node on FTT-10A Network
C decouple
C leak,SIGNAL
Vgate
NET_A
NET_B
Vcc
GND
"CHASSIS"
GND
C leak,CHASSIS
Figure 5.1 Parasitic Leakage Capacitances to Earth Ground
From this discussion, it is apparent that minimizing C
leak,SIGNAL
is very
important. By using 0.1µF or 0.01µF decoupling capacitors at each digital IC
power pin, Vcc and logic ground noise can be reduced. Logic ground can then be
used as a ground shield for other noisy digital signals and clock lines.
For example, in most FTT-10A nodes that use the Neuron 3120 Chip, the fastest
digital signal that needs to be routed across the PCB is the CLK2 line from the
Neuron Chip to the FTT-10A transceiver. If a two-layer PCB is being used, CLK2
can be routed to the transceiver pin with ground guard traces straddling the clock
trace on the top side of the board and a wide ground trace covering the underside of
the clock trace on the bottom side. If a four-layer PCB is being used, the clock
trace can be moved to an inner layer and guarded on all four sides. The CLK2
trace from the Neuron Chip to the FTT-10A transceiver should be as short as
practical, and in all cases no more than 2cm.
Since the Neuron 3150 Chip has an external memory interface bus, there are
many more traces that need to be guarded by logic ground in a Neuron 3150 Chip-
based FTT-10A node. In addition, the Vcc noise generated by the memory
interface and external ROM/RAM components requires more Vcc decoupling,