User`s guide

5-2 Design
Issues
EMI Design Issues
The high-speed digital signals associated with microcontroller designs can
generate unintentional electromagnetic interference (EMI). High-speed voltage
transitions generate RF currents that can cause radiation from a product if a
length of wire or piece of metal can serve as an antenna.
Products that use an FTT-10A transceiver together with a Neuron Chip will
generally need to demonstrate compliance with EMI limits enforced by various
regulatory agencies. In the USA, the FCC
6
requires that unintentional radiators
comply with Part 15 level “A” for industrial products, and level “B” for products
that can be used in residential environments. Similar regulations are imposed
in most countries throughout the world
7,8
.
In addition to the following discussion, designers of FTT-10A nodes are strongly
encouraged to read reference [11] for a good treatment of EMC. The EDN
Designer's Guide to EMC
12
also contains very good design advice.
Designing Systems for EMC (Electromagnetic Compatibility)
Careful PCB layout is important to ensure that an FTT-10A node will achieve the
desired level of EMC. A typical FTT-10A node will have several digital signals
switching in the 1-10MHz range. These signals will generate voltage noise near
the signal traces, and will also generate current noise in the signal traces and
power supply traces. The goal of good node design is to keep this voltage and
current noise from coupling out of the product's package.
It is very important to minimize the "leakage" capacitance from circuit traces in
the node to any external pieces of metal near the node, because this capacitance
provides a path for the digital noise to couple out of the product's package. Figure
5.1 shows the leakage capacitances to earth ground from a node's logic ground
(C
leak,GND
) and from a digital signal line in the node (C
leak,SIGNAL
). If the FTT-
10A node is housed inside a metal chassis, then that metal chassis will probably
have the largest leakage capacitance to other nearby pieces of metal. If the node is
housed inside a plastic package, then PCB ground guarding must be used to
minimize C
leak,SIGNAL
. Effective guarding of digital traces with logic ground
reduces C
leak,SIGNAL
significantly, which in turn reduces the level of common-
mode RF currents driven onto the network cable.
When a node is mounted near a piece of metal, especially metal that is earth
grounded, any leakage capacitance from fast signal lines to that external metal
will provide a path for RF currents to flow. When V
gate
is pulled down to logic
ground, the voltage of logic ground with respect to earth ground will increase
slightly. When V
gate
pulls up to Vcc, logic ground will be pushed down slightly
with respect to earth ground. As C
leak,SIGNAL
increases, a larger current flows
during V
gate
transitions, and more common-mode RF current couples into the
network twisted pair. This common-mode RF current can generate EMI in the
30-500MHz frequency band in excess of FCC/CISPR “B” levels even when
C
leak,SIGNAL
from a clock line to earth ground is less than 1pF. Guarding of
clock lines is essential for meeting Level “B” limits.