User`s guide

2-6 Electrical
Interface
Neuron Chip Communications Port (CP) Lines
The FTT-10A transceiver transmits and receives LonTalk network packets via the
Neuron Chip’s direct, single-ended mode interface using pins CP0 and CP1.
Neuron Chip data input pin CP0 is connected to the RXD pin of the FTT-10A
transceiver. Neuron Chip data output pin CP1 is connected to the TXD pin of the
FTT-10A transceiver. No buffering or other connections should be made to CP1.
The other Neuron Chip CP pins (CP2, 3, 4) are not connected to the FTT-10A
transceiver. The transceiver automatically detects activity on its TXD pin to enable
transmission, thus there is no connection to the Neuron Chip TXEN function on
CP2. The FTT-10A transceiver has a built-in bias circuit to prevent transmission
during the Neuron Chip reset process, when CP1 is not driven. The unused CP4
input should be connected to Vcc to prevent excess supply current draw in the
Neuron Chip input buffer. Table 2.5 summarizes connections between the Neuron
Chip Communication Port and the transceiver.
Table 2.5 Neuron Chip
Communication Port Connections
Neuron Chip Pin Neuron Chip Function Connect to
CP0 Data input FTT-10A RXD
CP1 Data output FTT-10A TXD
CP2 Transmit enable output Not connected
CP3 ~Sleep output Not connected
CP4 ~Collision Detect input Vcc
PC Board Layout Guidelines
An example of a PC board layout is shown in figure 2.3. The layout uses surface
mount (SMT) components on the top side of the PCB. The scale of the figures is
approximately 4X, but they are not intended for use as finished PCB artwork.
Variations on this suggested PCB layout are possible as long as the general
principles discussed later in this section (and in chapter 5) are followed. Through-
hole capacitors and diodes can be used, but SMT components will generally be
superior because of their lower series inductance.
Electrostatic discharge (ESD) and electromagnetic interference (EMI) are two of the
most important design considerations when laying out the PCB for a node. These
topics are discussed in general terms in chapter 5, and the specifics relating to PCB
layout issues are covered here.
Tolerance of ESD and other types of network transients requires good layout of the
power, ground and other node circuitry. In general, an ESD discharge current will
return to earth ground or other nearby metal structures. The node’s ground scheme
must be able to pass this ESD current between the network connection and the
node’s external ground connection without generating significant voltage gradients
across the node’s PCB. The low-inductance "Star" ground scheme illustrated in
figure 2.4 and discussed below accomplishes this task.