User`s guide

LONWORKS FTT-10A Transceiver User’s Guide 2-5
contact-discharge method for electrostatic discharge (ESD) in accordance with IEC
1000-4-2. Note that it is the operation of the Neuron Chip, and not of the FTT-10A
transceiver, which is affected at higher air-discharge levels when using the
modified circuit. It is recommended that the simplified circuit be used only
after determining that contact-discharge ESD protection is acceptable for
the application. If air-discharge ESD protection is required or the need
for it is undefined or unknown, then the circuit shown in figure 2.1 should
be used.
The clock, reset, and power supply bypass circuits in the modified circuit will not
represent a complete schematic, since they will vary depending on the Neuron Chip
type and application. For complete Neuron Chip application schematics and
information, refer to the Neuron Chip Databook
2,3
. See chapter 3 for mechanical
specifications and printed circuit board (PCB) footprint information.
In all of the interconnection schematics, capacitors C3 and C4 are used to provide
DC voltage isolation for the FTT-10A transformer when the transceiver is used on a
link power network, and may also be used to protect the transformer in the event of
a DC fault on the network. The capacitors are required to meet LonMark
interoperability guidelines. The capacitors are not needed on nodes that will be
connected exclusively to non-link power networks and do not require protection
against DC faults. Two polar capacitors are used to protect against the application
of DC of either polarity while providing total net capacitance of 11µF.
Alternatively, a single non-polar capacitor of 10µF may be used in either of the two
legs which connect to the network. The initial tolerance of the capacitor should
vary no more than ±20%, and degradation due to aging and temperature effects
should not exceed 20% of the initial minimum value.
Network Connection
The network connection (NET1 and NET2) is polarity insensitive and therefore
either of the two twisted pair wires can be connected to either of these network
connections. Details about network wiring are discussed in chapter 5.
Clock Input
The FTT-10A transceiver receives its clock input from the Neuron Chip via the
CMOS input CLK pin. This pin is driven by the CLK2 output of the Neuron Chip,
whether the Neuron Chip's oscillator or an external clock oscillator is used. The
CLK2 trace length should be kept to no more than 2cm (0.8”) to minimize noise
coupling.
The FTT-10A transceiver operates with an input clock of 5,10 or 20MHz. The
transceiver automatically detects the clock rate and configures internal circuitry
appropriately. Echelon has not qualified the FTT-10A transceiver for use with a
20MHz Neuron Chip and does not have a recommended board layout at this time;
please contact Echelon before starting a 20MHz design.
The accuracy of the input clock frequency to the Neuron Chip and
transceiver must be ±200 ppm or better; this requirement can be met with
a suitable crystal, but cannot be met with a ceramic resonator.