User`s guide

LONWORKS FTT-10A Transceiver User’s Guide 2-3
Figure 2.1 is not a complete schematic, since the clock, reset and power supply
bypass circuits will vary depending on the Neuron Chip type and application. For
complete Neuron Chip application schematics and information, refer to the Neuron
Chip Databook
2,3
. See chapter 3 for mechanical specifications and printed circuit
board (PCB) footprint information.
CP0
CP1
CLK2
CP2
CP3
CP4
Neuron Chip
(Partial)
+5V
FTT-10A
C1D2
+5V
D1
NET1
NET2
See Text
C3
C4
C2
PCB Spark
Gaps
D3
D4
RXD
NET_A
NET_B
VCC
T1
T2
GND
TXD
CLK
Figure 2.1 FTT-10A Transceiver Interconnection Using Spark Gaps
Table 2.3 FTT-10A Transceiver External Components
Name Value Comments
C1 0.1µF for +5VDC
decoupling
Power supply decoupling capacitor
for FTT-10A transceiver
C2 1000pF, 2kV, low
inductance
ESD snubber capacitor
C3,C4 22µF, +50V, polar DC blocking capacitors; see text
D1, D2, D3,
D4
BAV99 or 1N4148(x2) Transient clamping diodes;
BAV99LT1 (National), BAV99LT
(Sprague), MMBD120 (Motorola), or
equivalent
Some applications cannot use spark gaps due to the need for conformally coated or
potted PCBs. In figure 2.2 the spark gaps are replaced with encapsulated discharge
devices Z1 and Z2, which are connected to chassis ground. Each of these devices
has a discharge voltage of approximately 300 volts and introduces very little
capacitance (<1pF) to ground. Also note that diodes D3 through D6 are fast 1A
rectifiers which survive level 3 surge voltages (see chapter 5) and load the network
differentially with less than 150pF. These rectifiers are required to protect the
FTT-10A transceiver from surge voltages seen differentially across Net1 and Net2
as a result of asymmetric firing of the discharge devices in the presence of surge
voltages coupled