User`s guide

2-2 Electrical
Interface
Transceiver Pinout
The pinout of the FTT-10A transceiver is shown in table 2.1. Table 2.2 lists the
electrical specifications of the FTT-10A transceiver. All specifications apply over
the full operating temperature and supply voltage ranges unless otherwise noted.
Table 2.1 FTT-10A Transceiver Pinout
Name Pin Type Function
VCC 1 5V DC input
NET_B 2 Network port, polarity insensitive
NET_A 3 Network port, polarity insensitive
RXD 4 CMOS digital output capable of driving one
Neuron Chip and one HC-type input
Neuron Chip CP0
TXD 5 CMOS digital input with tri-state detection Neuron Chip CP1
CLK 6 Digital input, CMOS level Transceiver clock input from Neuron
Chip’s CLK2
T1 7 Bidirectional analog Used for ESD clamping & transient
protection
GND 8 Ground
T2 9 Bidirectional analog Used for ESD clamping & transient
protection
Table 2.2 FTT-10A Transceiver Electrical Specifications
Parameter Min Typ Max Units
Operating temperature range
excluding physical layer repeater
physical layer repeater
-40
0
+85
+85
degrees C
V
cc
input supply voltage 4.75 5 5.25 Volts
V
cc
input supply current
receive
transmit
5
20
mA
DC resistance between NET_A and NET_B 20
Ω
Transmitter raised cosine waveform peak-to-
peak amplitude into 52.3 Ω network termination
1.35 Volts
The preferred interconnection between the FTT-10A transceiver and a Neuron Chip
is shown in figure 2.1. This schematic has been tested for ESD under both the
preferred contact-discharge method and the alternate air-discharge method for
electrostatic discharge (ESD). It exceeds level 4 in accordance with IEC 1000-4-2,
and is recommended for all standard applications. (See Chapter 5 for more
details about IEC 1000-4-2). If the ESD protection requirements for the
application are undefined or unknown, then the circuit shown in figure
2.1 should be used.