Hardware Owner's manual
Table Of Contents
- Welcome
- Audience
- Related Documentation
- FTXL Hardware Overview
- FTXL Developer’s Kit Hardware
- FTXL Transceiver Hardware Interface
- FPGA Design for the FTXL Transceiver
- Working with the Altera Development Environments
- Using the Bring-Up Application to Verify FTXL Hardware Design
- Index
FTXL Hardware Guide 33
Read Handshake
Handshake (D0)
ready
A0 high -> D0
is handshake
R/W~ low -> read
Write length = 0x13
R/W~high -> write
A0 low -> D0 is
data
Figure 13. Timing Diagram for Writing the Length Byte
Figure 14 on page 34 shows a detailed timing diagram for writing the first two
bytes of the data. The figure also shows the read handshake for each byte of
data.