User`s manual

PCI 703 User Manual Eagle Technology - Data Acquisition
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Counters
The counter sub-system is supported by functions to Write, Configure and controlling the
gate. There are 3 counters and 1 frequency generator. Only the first two counters and the
frequency generator are available for the user. See the table below that shows the relation of
the counters and their assigned numbers.
Counter Assigned Number Description
0 0 Counter 0
1 1 Counter 1
2 <Not Used> A/D Timing
3 2 Frequency Out Counter
Table 4-1 Counter Assignment
Writing the initial counter value
A single call is necessary to write a counter’s initial load value.
API-CALL
Long EDRE_CTWrite(ulng Sn, ulng Ct, ulng Value)
The serial number, counter-number, and a value must be passed by the calling function. A
return code will indicate if any errors occurred.
ACTIVEX CALL
Long EDRECTX.Write(long Port, ulng Value)
The port number and value to be written needs to be passed and the returned value holds an
error or the value read. If the value is negative an error did occur.
Configuring a counter
A single call is necessary to configure a counter.
API-CALL
Long EDRE_CTConfig(ulng Sn, ulng Ct, ulng Mode, ulng Type, ulng ClkSrc, ulng
GateSrc)
The serial number, counter-number, mode, type, clock source and gate source is needed to
specify a counter’s configuration. A return code will indicate if any errors occurred.
ACTIVEX CALL
Long EDRECTX.Configure(long ct, long mode, long type, ulng source, ulng gate)
The counter-number, mode, type, clock source and gate source is needed to specify a
counter’s configuration. A return code will indicate if any errors occurred.
Only the counter mode, clock source and type parameters are used by the PCI703. The table
below shows the options for each parameter.
Parameter Description
Sn Serial Number
Ct Counter Number:
0 : Counter 0
1 : Counter 1
2 : Frequency Out Counter
Mode 0 : PULSE
1 : TOGGLE
Invalid parameter for counter 2
Type Interrupt on TC:
0 : Disabled
1 : Enabled
This bit will only generate a interrupt at the interrupt sub-system. The
interrupt sub-system must also be setup to generate a PCI Bus
interrupt.
Source 0 : 20MHz internal clock
1 : 100KHz internal clock
2 : External clock on CPCTRx pin<invalid for counter 2>