Service Manual Part 2

CIRCUIT DESCRIPTION
4-8
September 2001
Part No. 001-5100-001
initialized by the microcontroller through the SPI bus.
For any functionality of the ADSIC to exist, including
initial programming, the reference clock must be
present.
SBI is a programming data line for the ABACUS.
This line is used to configure the operation of the
ABACUS and is driven by the ADSIC. The microcon-
troller programs many of the ADSIC operational
features through the SPI interface. There are 36
configuration registers in the ADSIC of which 4
contain configuration data for the ABACUS. When
these particular registers are programmed by the
microcontroller, the ADSIC in turn sends this data to
the ABACUS through the SBI.
DIN and DIN* are the data lines in which the I
and Q data words are transferred from the ABACUS.
These signals make up a differentially encoded current
loop. Instead of sending TTL-type voltage signals, the
data is transferred by flowing current one way or the
other through the loop. This helps reduce internally
generated spurious emissions on the RF Board. The
ADSIC contains an internal current loop decoder
which translates these signals back to TTL logic and
stores the data in internal registers.
The ADSIC performs digital IF filtering and
frequency discrimination on the signal, sending the
baseband demodulated signal to the DSP. The internal
digital IF filter is programmable with up to 24 taps.
These taps are programmed by the microcontroller
through the SPI interface.
The DSP processes this data through the SSI
serial port. This is a six-port synchronous serial bus.
The ADSIC transfers the data to the DSP on the TxD
line at a rate of 2.4 MHz. This is clocked synchro-
nously by the ADSIC which provides a 2.4 MHz clock
on SCKT. In addition, a 20 kHz interrupt is provided
on TFS to signal the arrival of a data packet. This
means a new I and Q sample data packet is available to
the DSP at a 20 kHz rate which represents the
sampling rate of the received data. The DSP then
processes this data to extract audio, signaling, and
other information based on the 20 kHz interrupt.
In addition to the SPI programming bus, the
ADSIC also contains a parallel configuration bus. This
bus is used to access registers mapped into the DSP
memory. Some of these registers are used for addi-
tional ADSIC configuration controlled directly by the
DSP. Some of the registers are data registers for the
speaker D/A. Analog speaker audio is processed
through this parallel bus where the DSP outputs the
speaker audio digital data words to this speaker D/A.
In addition, an analog waveform is generated which is
output to SDO (Speaker Data Out).
In conjunction with speaker D/A, ADSIC
contains a programmable attenuator to set the rough
signal attenuation. However, the fine levels and differ-
ences between signal types are adjusted through the
DSP software algorithms. The speaker D/A attenuator
setting is programmed by the microcontroller through
the SPI bus.
The ADSIC provides an 8 kHz interrupt to the
DSP on IRQB for processing the speaker data
samples. This 8 kHz signal must be enabled through
the SPI programming bus by the microcontroller and is
necessary for any audio processing to occur.
4.4.4 TRANSMIT SIGNAL PATH
The ADSIC contains an analog-to-digital (ADC)
converter for the microphone. The microphone path in
the ADSIC also includes an attenuator that is
programmed by the microcontroller through the SPI
bus. The microphone input in the ADSIC is on pin
MAI (U3-19). The microphone ADC converts the
analog signal to a series of data words and stores them
in internal registers. The DSP accesses this data
through the parallel data bus. As with the speaker data
samples, the DSP reads the microphone samples from
registers mapped into its memory space. The ADSIC
provides an 8 kHz interrupt to the DSP on IRQB for
processing the microphone data samples.
The DSP processes these microphone samples
and generates and mixes the appropriate signaling and
filters the resultant data. This data is then transferred
to the ADSIC on the DSP SSI port. The ADSIC gener-
ates a 48 kHz interrupt so that a new sample data
packet is transferred at a 48 kHz rate and sets the
transmit data sampling rate at 48 ksps. These samples
are then input to a transmit D/A which converts the
data to an analog waveform. This waveform is the
modulation signal from the ADSIC and is connected to
the VCO on the RF Board.
DIGITAL BOARD (CONT’D)