Specifications

ADDITIONAL LOCAL IO FUNCTIONS
PP 41x/03x 9-11
9.9 Interrupt Configuration Register
This register is at I/O address 21Dh.
7 6 5 4 3 2 1 0
IPMI
INTERRUPT
STATUS
PIT
INTERRUPT
STATUS
PIT
INTERRUPT
ENABLE
M66EN
INTERRUPT
FLAG
M66EN
INTERRUPT
ENABLE
ENUM#
STATUS
ENUM#
INTERRUPT
ENABLE
ENUM#
ROUTING
Bit 0: CompactPCI ENUM# Interrupt Routing (Read/Write)
This bit selects which interrupt the CompactPCI ENUM# signal is routed to. This interrupt is only
relevant when the board is System Controller.
0 = NMI
1 = PCI bus interrupt
Bit 1: CompactPCI ENUM# Interrupt Enable (Read/Write)
0 = disable Interrupt generation
1 = enable Interrupt generation
Bit 2: CompactPCI ENUM# Pin Status (Read Only)
0 = ENUM# is not asserted
1 = ENUM# is asserted
Bit 3: CompactPCI M66EN High-Low Transition Interrupt Enable (Read/Write)
When the board is System Controller it monitors the CompactPCI M66EN signal for high to low
transitions during normal operation. A PCI bus interrupt may be generated if such a transition
occurs. This bit enables that interrupt. The setting of bit 0 has no effect on this interrupt.
0 = transition interrupt is disabled
1 = transition interrupt is enabled
Bit 4: CompactPCI M66EN High-Low Transition Flag (Read/Clear)
This flag can be cleared by writing to the register with a zero in this bit position.
0 = clear flag
1 = leave flag unchanged
Bit 5: PIT Interrupt Enable (Read/Write)
This bit allows an interrupt to be generated when the PIT_INT signal from the 6300ESB ICH
Periodic Interrupt Timer (PIT) changes state.
0 = PIT interrupt is enabled
1 = PIT interrupt is disabled
Bit 6: PIT Interrupt Flag (Read/Clear)
This flag can be cleared by writing to the register with a zero in this bit position.
0 = clear flag
1 = leave flag unchanged
Bit 7: IPMI Interrupt Status (Read Only)
0 = IPMI interrupt is not asserted
1 = IPMI interrupt is asserted