Specifications

INTRODUCTION
1-2 PP 41x/03x
1.2 The PP 41x/03x - Main Features
The PP 41x/03x is a member of the Concurrent Technologies range of single-board computers for
the CompactPCI bus architecture. It has been designed as a powerful single board computer
based upon the Intel Core Duo or the Intel Core 2 Duo processor, the Intel® E7520 and 6300ESB
chipset and three Intel® 82573L Gigabit Ethernet controllers. It also provides two IEEE 1386.1
PMC sites (one of which also supports XMC), optional on-board mass storage, and interfaces for
standard PC-AT based peripherals.
1.2.1 Central Processor
The central processor used on this board is either an Intel Core Duo processor, operating internally
at 1.66 GHz or 2.0 GHz or an Intel Core 2 Duo processor, operating internally at 2.16 GHz.
Both processor types have two high performance execution cores. Those in the Core Duo
processor are derived from the Intel Pentium M processor, whereas those in the Core 2 Duo
processor are based on the latest Intel Core architecture. The 64-bit frontside bus is connected to
the memory controller at 667 MHz to provide a maximum transfer bandwidth of 5.3 Gbytes/s. The
processor is capable of addressing 4 Gbytes of physical memory all of which is cacheable, and 64
Terabytes of virtual memory.
The Intel Core Duo and Core 2 Duo processors are upwardly code-compatible with the other
members of the x86 family of microprocessors. They have in-built floating point coprocessors for
compatibility with 486 and 386/387 designs. The Core 2 Duo processor also supports Intel 64
architecture (i.e. 64-bit operation).
Elsewhere in this manual the processor is referenced as the Intel Core Duo processor regardless
of the exact CPU chip being used.
1.2.2 Cache Memories
The Level 1 and Level 2 caches are both implemented on the processor die for maximum
performance. Each of the two execution cores has its own Level 1 cache and they share a
common Level 2 cache. The Level 1 cache is organized as 32 Kbytes of instruction cache and 32
Kbytes of data cache. The Level 2 cache stores both instructions and data. It operates at the core
frequency and is based on Intel’s Advanced Transfer Cache architecture. The Core Duo processor
has 2 Mbytes of Level 2 cache, whereas the Core 2 Duo processor has 4 Mbytes of Level 2 cache.
1.2.3 Chipset
The PP 41x/03x uses the Intel E7520 and 6300ESB chipset. This is comprised of the E7520
Memory Controller Hub (MCH) and the 6300ESB I/O Controller Hub (ICH). They respectively
provide North Bridge + PCI Express controller and South Bridge + PCI bus controller functionality.
The E7520 MCH interfaces to the CPU’s host bus. It provides a dual-channel DDR2 SDRAM
memory controller, three configurable PCI Express links and a high speed Hub Interface 1.5 which
connects to the 6300ESB ICH. It supports concurrent CPU, memory, PCI Express and Hub
Interface bus operations.
The 6300ESB ICH provides a 66 MHz 64-bit PCI or PCI-X bus for supporting high performance
PCI devices. It also provides a 33 MHz 32-bit PCI bus. The Hub Interface supports a maximum
transfer bandwidth of 266 Mbytes/s.
The 6300ESB ICH also provides a variety of peripheral functions including Serial ATA (SATA)
controllers, EIDE controllers, USB 2.0 and 1.1 controllers, LPC (Low Pin Count) Bus bridge,
IOAPIC interrupt controller, Real Time clock (RTC), two serial ports and other legacy PC-AT
architectural functions.
The LPC Bus is used to connect to the Firmware Hub (FWH), the control and status registers and
to the PC87391 Super I/O Controller on the companion AD PP5/001-4xU Transition Module. This
device implements a floppy disk controller, a parallel port and two additional serial ports.