Specifications

SYSTEM MANAGEMENT
11-4 PP 41x/03x
11.3 ECC Error Logging
The E7520 MCH includes hardware for detecting and correcting single-bit ECC errors and for
detecting multi-bit ECC errors. Both types of ECC error can be recorded by the BIOS via the DMI
Event Log (Advanced | DMI Event Logging | View DMI event log).
11.3.1 Single-bit ECC Errors
Single-bit ECC errors are a rare occurrence in normal operation. The chipset will detect single bit
errors during memory reads and automatically pass the corrected data to the CPU instead.
Single-bit ECC errors are recorded by the BIOS so that the user can be made aware of any
unusual behavior.
11.3.2 Multi-bit ECC Errors
Multi-bit ECC errors are a very rare occurrence in normal operation. The chipset can detect multi-
bit errors, but is unable to make corrections; therefore the BIOS will halt the board to prevent
invalid code or data being processed.
In the unlikely event that a board halts unexpectedly, the user should examine the event log to
determine whether a multi-bit ECC error was the cause.
11.3.3 Background ECC Event Logging
The BIOS code responsible for recording ECC errors remains resident in System Management
memory after the operating system loads. This code is invisible to the operating system and
consumes no CPU cycles or memory resources, unless triggered.
The ECC error logging code is triggered by a System Management Interrupt, which is generated by
the hardware ECC logic. The error logging code minimizes its impact on the operating system by
only recording one single-bit ECC event per hour.
Multi-bit ECC errors will always cause the board to halt, regardless of whether ECC Event Logging
is enabled.
11.3.4 Memory Scrubbing
The E7520 MCH includes hardware for reading all populated locations in memory space and
correcting any single-bit ECC errors that are found. This activity takes place during periods of
memory bus inactivity and hence does not impact performance. The entire 4 Gbyte memory space
can be scrubbed in approximately 6 hours. The rationale for doing this is to remove soft memory
errors while they are still correctable (i.e. single-bit) and before they deteriorate into non-
correctable (i.e. multi-bit) errors.