Specifications

PC BIOS
10-10 PP 41x/03x
10.4.8 Peripheral Mode Window-Size Limitations
The CompactPCI bridge forms PCI addresses by concatenating the least significant bits from the
CPU generated address and the most significant bits from the translation base address; the
contribution from each part is fixed and depends upon the window type. However, the BIOS always
aligns base addresses according to their resource size, to achieve optimal packing. If a window is
defined to be smaller than the translation base address granularity, the BIOS assigned base
address may result in configuration where offset 0h into the resource window does not map to
offset 0h from the translation base address. The example below illustrates this point:
Configured I/O window size: 256 bytes
Bridge window granularity: 4096 bytes
BIOS assigned base address: 12345600h (i.e. 256 byte aligned)
Translation base address: ABCDE000h (i.e. 4096 byte aligned)
Address generated by bridge: ABCDE6xxh (xx = offset into window)
In this example, accesses to offset 0h into the window result in accesses to offset 600h from the
translated base address.
10.4.8.1 I/O Windows
For I/O windows, the translation base address granularity, and hence minimum practical size, is
4Kbytes.
10.4.8.2 Memory Mapped Windows
For memory mapped windows, the translation base address granularity, and hence minimum
practical size, is 1Mbyte.