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E-mail: info@gocct.com http://www.gocct.com

Concurrent Technologies Plc

4 Gilberd Court

Newcomen Way

Colchester, Essex CO4 9WN

United Kingdom

Tel: (+44) 1206 752626

Fax: (+44) 1206 751116

Concurrent Technologies Inc

3840 Packard Road

Suite 130

Ann Arbor, MI 48108

USA

Tel: (734) 971 6309

Fax: (734) 971 6350

Technical Reference Manual

for PP 41x/03x CompactPCI

Intel

Core Duo

Processor

Intelligent Dual PMC Carrier

Manual Order Code 560 0024 Rev 04 January 2007

Summary of content (128 pages)

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Technical Reference Manual for PP 41x/03x CompactPCI® Intel® Core Duo® Processor Intelligent Dual PMC Carrier Manual Order Code 560 0024 Rev 04 January 2007 Concurrent Technologies Inc 3840 Packard Road Suite 130 Ann Arbor, MI 48108 USA Tel: (734) 971 6309 Fax: (734) 971 6350 E-mail: info@gocct.com Concurrent Technologies Plc 4 Gilberd Court Newcomen Way Colchester, Essex CO4 9WN United Kingdom Tel: (+44) 1206 752626 Fax: (+44) 1206 751116 http://www.gocct.
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NOTES Information furnished by Concurrent Technologies is believed to be accurate and reliable. However, Concurrent Technologies assumes no responsibility for any errors contained in this document and makes no commitment to update or to keep current the information contained in this document. Concurrent Technologies reserves the right to change specifications at any time without notice.
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GLOSSARY OF TERMS AC’97 ............................... Audio CODEC 1997 ACPI ................................ Advanced Configuration and Power Interface APIC ................................ Advanced Programmable Interrupt Controller ATA.................................. AT Attachment BIOS ................................ Basic Input Output System BMC................................. Baseboard Management Controller CMOS .............................. Complementary Metal Oxide Semiconductor CODEC...........
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REVISION HISTORY Revision 01 02 03 04 iv Summary of Changes First Release Corrected J3 and J5 pin-out tables; changed AD PP5/001-3x references to AD PP5/001-4xU Changes for Rev B board; updated default positions on 3 switches: ‘PMC 2 PCI-X Enable’, ‘PMC 2 PCI Speed’ and ‘BIOS Defaults’; updated SM722 PCI Device ID Changes for Rev C board, added E-Series details, added Core 2 Duo support, added AD PP5/003 RTM details, various minor corrections and clarifications.
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TABLE OF CONTENTS 1 INTRODUCTION ...................................................................................... 1-1 1.1 General .....................................................................................................................................1-1 1.2 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.2.6 1.2.7 1.2.8 1.2.9 1.2.10 1.2.11 1.2.12 1.2.13 1.2.14 1.2.15 1.2.16 1.2.17 The PP 41x/03x - Main Features .........................................................................................
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2.10 CompactPCI Operating Mode Selection .................................................................................2-15 2.11 2.11.1 2.11.2 2.11.3 Reset Sources ........................................................................................................................2-16 CompactPCI Reset .................................................................................................................2-17 External Reset ...................................................................
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.3.6 7.3.7 Field Replaceable Unit Inventory Data .....................................................................................7-4 Watchdog..................................................................................................................................7-4 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.4.1 7.4.4.2 7.4.4.3 7.4.4.4 7.4.4.5 7.4.4.6 7.4.4.7 7.4.4.8 7.4.4.9 7.4.4.10 7.4.4.11 Supported Commands ...........................................................................................
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9.10.1 9.10.2 9.10.3 SMIC Data Register ................................................................................................................9-12 SMIC Control/Status Register.................................................................................................9-12 SMIC Flags Register...............................................................................................................9-12 9.11 P.O.S.T. LED / Speaker............................................................
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A.5.2 A.5.3 A.5.4 A.5.5 A.5.6 A.5.7 A.5.8 A.5.9 A.5.10 CompactPCI Interface (J2) Pin-outs ........................................................................................ A-7 CompactPCI Interface (J3) Pin-outs ........................................................................................ A-8 CompactPCI Interface (J5) Pin-outs ........................................................................................ A-9 On-Board Mass Storage Option Connector (P5) Pin-outs ...................
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TABLE OF FIGURES x Figure 1-1 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 2-8 Figure 2-9 Figure 2-10 Figure 2-11 Figure 2-12 Figure 2-13 Figure 2-14 Figure 2-15 Figure 2-16 Figure 2-17 Figure 6-1 Figure 6-2 Figure 7-1 Figure 10-1 Figure 10-2 Figure 10-3 Overview..........................................................................................................................1-1 Default Jumper and Switch Settings...............................................
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TABLE OF TABLES Table 2-1 Table 5-1 Table 6-1 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 9-1 Table 10-1 Table 10-2 Table 11-1 Reset Configuration Options..........................................................................................2-16 Ethernet Interface Identification .......................................................................................5-1 Serial Port Numbering .....................................................................................................
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This page has been left intentionally blank xii PP 41x/03x
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1 1.1 INTRODUCTION General This manual is a guide and reference handbook for engineers and system integrators who wish to use the Concurrent Technologies’ PP 41x/03x ultra high-performance Intel® Core™ Duo or Intel® Core™ 2 Duo processor single board computer. The board has been designed for high-speed multiprocessing applications using a PC-AT™ architecture operating in a CompactPCI Bus environment.
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INTRODUCTION 1.2 The PP 41x/03x - Main Features The PP 41x/03x is a member of the Concurrent Technologies range of single-board computers for the CompactPCI bus architecture. It has been designed as a powerful single board computer based upon the Intel Core Duo or the Intel Core 2 Duo processor, the Intel® E7520 and 6300ESB chipset and three Intel® 82573L Gigabit Ethernet controllers. It also provides two IEEE 1386.
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INTRODUCTION 1.2.4 SDRAM The SDRAM controller within the E7520 MCH supports dual DDR2 400MHz memory channels with ECC data protection. These provide a maximum memory transfer bandwidth of 6.4 Gbytes/s. The memory is implemented with DDR2 Registered ECC SODIMM modules. Two 200-pin SODIMM sockets are provided, one per channel. The board will accept modules having a capacity up to 2 Gbytes each. Hence a maximum of 4 Gbytes of memory may be fitted to the board. 1.2.
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INTRODUCTION 1.2.11 Ethernet Controllers Three Intel® 82573L Gigabit Ethernet controller are used to provide high performance PCI Express to Ethernet interfaces. All three channels support 10, 100 and 1000 Mbits/s operation. One channel is routed to a front panel RJ45 connector; the other two channels are routed to the CompactPCI J3 connector. The board can either support PICMG® 2.16 backplane networking or rear panel Ethernet. This is specified by an ordering option.
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INTRODUCTION 1.3 Rear Transition Module Peripheral Functions Three Rear Transition Modules (RTMs) may be used with the PP 41x/03x board, namely the AD PP5/001-4xU, the AD PP5/002-0x and the AD PP5/003-0x. Each of these RTMs provides a different set of peripheral functions. 1.3.1 AD PP5/001-4xU Peripheral Functions The AD PP5/001-0x (or AD PP5/001-0xU) RTM was originally designed for use with the PP 31x/01x family of boards.
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INTRODUCTION 1.3.3 AD PP5/003-0x Peripheral Functions The AD PP5/003-0x RTM provides flexible PMC site rear I/O management by the use of Peripheral Interface Modules (PIMs). It provides the following interfaces: • • • • • • • • • • • • 1-6 PIM site for PMC site 1 rear I/O. PIM site for PMC site 2 rear I/O. 68-pin in-board connector for PMC site 2 SCSI. Two Serial ATA (SATA) interfaces. One Gigabit Ethernet port. Two USB ports. One RS232 serial interface (COM2).
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INTRODUCTION 1.4 Additional Board Options The PP 41x/03x board may be ordered with one of a few factory fitted configuration options, in particular the Ethernet (on J3 connector): • • Configured for PICMG 2.16 backplane networking Configured for rear panel Ethernet via connectors (on RTM) Two mezzanine mass storage options are available, namely: • • A 2.
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INTRODUCTION 1.5 Extended Temperature Options All variants of the board are qualified for the standard operating and storage temperature ranges indicated in Section A.2.1. Some variants of the board are available which offer a wider range of operating and storage temperatures, but certain board features are no longer available with these variants. In particular the option for on-board mass storage using a 2.5 inch hard disk drive is not supported for the extended temperature specifications.
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INTRODUCTION 1.6 Compliance to RoHS 2002/95/EC This product is offered in a form which complies to the RoHS 2002/95/EC directive. The European Union RoHS 2002/95/EC directive restricts the use of six materials in electronic components and assemblies. Specifically, these materials are Lead (Pb), Mercury (Hg), Cadmium (Cd), Hexavalent Chromium (Cr VI), Polybrominated Biphenyls (PBB) and Polybrominated Diphenyl Ethers (PBDE). Concurrent Technologies is committed to compliance to the RoHS directive.
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INTRODUCTION This page has been left intentionally blank 1-10 PP 41x/03x
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2 2.1 HARDWARE INSTALLATION General This chapter contains general information on unpacking and inspecting the PP 41x/03x after shipment, and information on how to configure board options and install the board into a CompactPCI chassis. CAUTION: It is strongly advised that, when handling the PP 41x/03x and its associated components, the user should at all times wear an earthing strap to prevent damage to the board as a result of electrostatic discharge. CAUTION: The heatsink used on the 2.0 GHz or 2.
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HARDWARE INSTALLATION 2.2 Unpacking and Inspection Immediately after the board is delivered to the user’s premises the user should carry out a thorough inspection of the package for any damage caused by negligent handling in transit. CAUTION: If the packaging is badly damaged or water-stained the user must insist on the carrier’s agent being present when the board is unpacked. Once unpacked, the board should be inspected carefully for physical damage, loose components etc.
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HARDWARE INSTALLATION 2.
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HARDWARE INSTALLATION 2.4 Front Panel Indicators and Controls When installing or removing the board for the first time, or when checking its operation, it can be very useful to note the behavior of the LEDs on the front panel. Figure 2-2 shows the location of the LEDs, and their purpose is outlined below. Figure 2-2 Front Panel Indicators and Controls 2.4.1 Run LED (R) Green The run LED indicates that activity is occurring on the LPC bus or the 32-bit PCI bus.
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HARDWARE INSTALLATION 2.4.8 Switch (SW) A pushbutton switch is recessed behind the front panel, and provides a means of generating a reset or NMI to the board. The reset or NMI function is selected by the setting of the Front Panel Switch Function switch shown in Figure 2-3. Figure 2-3 Front Panel Switch Function Selecting the Reset position setting will cause the board to be reset when the front panel switch is operated.
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HARDWARE INSTALLATION 2.5 On-board CompactFlash Site A CompactFlash site is provided on the PP 41x/03x board. The site fully supports Type I modules. A Type II module or a MicroDrive may be fitted, but the user should be aware that these are 5.0mm tall and therefore encroach into the clearance zone between the PP 41x/03x board and PMC module. This may cause an interference problem if the PMC module also encroaches into this clearance zone.
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HARDWARE INSTALLATION 2.6 Battery Installation/Replacement The on-board Real-Time Clock and CMOS memory used by the PC BIOS firmware are powered by a 3.3V Lithium battery when the board is powered OFF. It is advisable, for the battery to be fitted prior to using the board. Figure 2-5 shows how to do this. One battery is supplied with the board, but it is not normally fitted.
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HARDWARE INSTALLATION 2.7 Installation of On-Board Mass Storage If an on-board mass storage option has been ordered, it will be necessary to install the option at this time. The mass storage option plugs into connector P5 and is secured via screws and spacers using the four mounting holes as shown in Figure 2-6 below.
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HARDWARE INSTALLATION 2.7.1 Hard Disk Storage Kit (AD CP1/DR1) The option kit comprises: • • • • A 2.5 inch EIDE disk drive A ribbon cable assembly Four M3 x 10mm screws Four M3 x 5mm spacers The ribbon cable assembly has a 50-way connector at one end and a 44-way connector at the other end. The 50-way connector plugs into the disk drive and the 44-way plugs into P5 on the PP 41x/03x. 1) Plug the 50-way connector into the disk drive as shown in Figure 2-7 below, note the orientation.
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HARDWARE INSTALLATION 2.7.2 CompactFlash Storage Kit (AD 200/001) The option kit comprises: • • A CompactFlash carrier module with attached ribbon cable Four M3 panhead screws CompactFlash Carrier Module CompactFlash Sites Site 2 Site 1 Pillars P5 Connector Figure 2-8 CompactFlash Carrier Module Installation To install the CompactFlash carrier module, follow these instructions: 1) The M3 panhead screws may be loosely screwed into the end of the pillars, if so unscrew them.
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HARDWARE INSTALLATION 2.8 Adding or Replacing DRAM Modules The PP 41x/03x accepts standard 200-pin DDR2-400 Registered ECC SODIMM modules populated with 1.8V PC3200 DDR2 SDRAM. Two sockets are provided and will accommodate modules up to 2 Gbytes capacity each. Identical SODIMMs must be fitted in both sockets. Consult your distributor or Concurrent Technologies directly for details of suitable SODIMMs. CAUTION: The PP 41x/03x does not support 64-bit non-ECC DDR2 SODIMM modules.
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HARDWARE INSTALLATION 2.9 Installing or Removing a PMC Module The PP 41x/03x board provides jumper selectable 3.3V or 5V V(I/O) to PMC site 1 and fixed 3.3V V(I/O) to PMC site 2. Before installing a PMC module check that its V(I/O) requirements match those of the site. CAUTION: Do not fit PMC modules designed for 5V V(I/O) only in PMC site 2. Doing so may cause damage to the module or the PP 41x/03x.
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HARDWARE INSTALLATION Figure 2-12 PP 41x/03x PMC Site 2 Installation Diagram 2-13
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HARDWARE INSTALLATION 2.9.1 PMC Site 2 Bus Speed and Mode Selection The PCI bus connecting to PMC Site 2 can operate at various bus speeds and modes, namely, 33 MHz PCI, 66 MHz PCI, 66 MHz PCI-X and 100 MHz PCI-X. The bus speed and mode is determined by the settings of two option switches. These switches are shown in Figure 2-13. Switch 1 should normally be in the ON position. This forces the bus to operate in PCI mode. If a PCI-X capable PMC module is fitted, Switch 1 should be set to the OFF position.
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HARDWARE INSTALLATION 2.10 CompactPCI Operating Mode Selection This is normally automatic and depends only on what type of slot the board is installed into, as detailed below: Slot System Controller Bussed Peripheral Non-Bussed Peripheral Mode System Controller Peripheral or Satellite Satellite A switch is provided to force Satellite mode operation in any slot. The settings are shown in Figure 2-14. In Satellite mode the board cannot communicate on the CompactPCI bus.
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HARDWARE INSTALLATION 2.11 Reset Sources In addition to the front panel switch described in Section 2.4.8, the board may be reset from several external sources, as described below. Table 2-1 outlines how board and system resets can be achieved using the available jumper options.
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HARDWARE INSTALLATION 2.11.1 CompactPCI Reset The CompactPCI Reset signal is generated by the System Controller and is routed to all bussed Peripheral slots. If the board is in Satellite mode, it may be preferable for it to ignore the CompactPCI Reset signal. A switch is provided to facilitate this choice. The settings are shown in Figure 2-15.
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HARDWARE INSTALLATION 2.11.2 External Reset When the PP 41x/03x board is used with an AD PP5/001-4xU, AD PP5/002-xx or AD PP5/003-xx Rear Transition Module, a local (board-level) reset may be generated from a connector on the RTM (see that board’s Technical Reference Manual for details). The action of that connector input is controlled on the PP 41x/03x by the External Reset switch shown in Figure 2-16. This switch has no function when the PP 41x/03x is used without an RTM.
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HARDWARE INSTALLATION 2.11.3 CompactPCI Push Button Reset The Push Button Reset signal available on the J2 connector (PRST#) will cause a board reset if the board is in the System Controller slot. This input can be driven from an open collector TTL output (or discrete transistor) or normally open switch/relay contacts. To initiate the reset pull this input to 0V. This input is filtered and protected from overshoots/undershoots so no external contact debouncing is required.
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HARDWARE INSTALLATION 2.12 Installation and Power-up Before the board is installed in a CompactPCI chassis, check the following points: • The backplane V(I/O) configuration. The PP 41x/03x board supports either 5V or 3.3V V(I/O) automatically. Some CompactPCI backplanes are pre-wired for a particular voltage and others can be configured by the user. For 66 MHz CompactPCI operation the voltage must be 3.3V. WARNING: V(I/O) must be wired on the backplane.
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HARDWARE INSTALLATION 2.12.1 Non Hot Swap Procedure - Installing The board is installed and powered up as follows: a) Make sure that system power is turned OFF. b) Slide the board into the designated slot, making sure that the board fits neatly into the runners. c) Push the board into the card-cage until the J1 ... J5 connectors are firmly located. Use the injector/ejector handles for the final push. d) Screw the ejector handle retaining bolts into the holes in the chassis.
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HARDWARE INSTALLATION 2.12.4 Hot Swap Procedure - Removing To remove the board: a) Open the lower ejector handle and wait for the blue “Hot Swap” LED to switch on. This may take a few seconds. Newer handles require a red button to be pressed in order to open the handle. b) Open both ejector handles and remove the board.
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3 SOFTWARE INSTALLATION In most cases, installing operating system software on the PP 41x/03x board follows the same sequence as installing on a PC. However, there are some additional points to note. The sections below summarize the special actions required for a few common operating systems. 3.1 Starting up for the first time Many operating systems running on the board will want to use the standard Real-Time Clock hardware.
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SOFTWARE INSTALLATION 3.2 Bootloading from CD-ROM Operating systems that install on the target hardware will generally install from CD-ROM, or may require both a CD-ROM and floppy disk. Boot-loading from floppy disk requires no special steps other than to connect the drive using an appropriate cable. To boot-load from CD-ROM, use the following procedure: a) While the BIOS is running its memory test, press the key. b) Wait for the pop-up boot device menu to be displayed.
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SOFTWARE INSTALLATION 3.3 Installing Microsoft® Windows® Operating Systems Installing these operating systems on the PP 41x/03x is generally very similar to installing them on a desktop PC. However, Concurrent Technologies also offers a Board Support Package on CDROM (part number CD WIN/PC1-L0) which provides installation and configuration information, including appropriate drivers. Please refer to your supplier for further details or to obtain this package.
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SOFTWARE INSTALLATION 3.4 Installing RedHat® Linux® Installing these operating systems on the PP 41x/03x is generally very similar to installing them on a desktop PC. However, in order to package all the required drivers in a convenient form for installation on a range of Concurrent Technologies boards, the company also offers a Board Support Package on CD-ROM (part number CD LNX/PC1-L0) which provides installation and configuration information, including appropriate drivers.
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4 MASS STORAGE INTERFACES The PP 41x/03x board has four interfaces that can be used to attach mass storage devices: • • • Two Serial ATA (SATA) interfaces, which are accessible via the CompactPCI J5 connector. The Primary EIDE (ATA100) interface supporting the on-board Mass Storage option kits. The Secondary EIDE (ATA100) interface connected to the on-board Compact Flash site. The order in which the PC BIOS firmware tries to boot-load from these drives can be changed via the BIOS Setup screen for Boot.
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MASS STORAGE INTERFACES This page has been left intentionally blank 4-2 PP 41x/03x
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5 ETHERNET INTERFACES The PP 41x/03x board is fitted with three independent 1 Gigabit Ethernet interfaces, implemented with three Intel 82573L controllers. One of these devices provides the front panel Ethernet interface, the other two provide the rear Ethernet interfaces. The rear Ethernet interfaces can connect in different ways, depending primarily on the build configuration of the board. This configuration is indicated by the first digit of the board name suffix; refer to the data sheet for details.
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ETHERNET INTERFACES This page has been left intentionally blank 5-2 PP 41x/03x
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6 OTHER INTERFACES Many additional standard interfaces are provided on the PP 41x/03x board. These interfaces consist primarily of those found in a regular desktop or mobile PC, and are outlined below. 6.1 Serial Ports One RS232 serial interface is always available on the PP 41x/03x board. This interface connects via the front panel Console connector. A splitter cable, part number CB 26D/125-00, is required to access this interface. A second RS232 serial interface is available on the J5 connector.
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OTHER INTERFACES 6.1.1 PC BIOS Serial Console With some operating systems, or in some applications, it is preferable to use a serial terminal as an operator console device for the board. In other cases, a standard VGA screen and PC keyboard will be required. The PP 41x/03x can be configured for operation with either a VGA screen or keyboard or with a serial console. A board switch selects the console mode, as shown in Figure 6-1 below.
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OTHER INTERFACES 6.1.2 PC BIOS Serial Console Port When the PC BIOS is configured to use a serial port for its console, either COM1 or COM2 (on the AD PP5/001-4xU or AD PP5/002-0x Transition Module) can be selected, using the board switch shown in Figure 6-2.
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OTHER INTERFACES 6.2 Keyboard and Mouse Ports The PP 41x/03x provides PS/2™ type keyboard and mouse interfaces via the front panel Console connector. This connector also provides a USB interface, which may be used to connect a USB keyboard or mouse. A splitter cable, part number CB 26D/125-00, is required to access these interfaces. 6.3 Graphics (VGA) Controller The PP 41x/03x board contains a Silicon Motion SM722 graphics controller.
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7 7.1 INTELLIGENT PLATFORM MANAGEMENT INTERFACE Introduction The Intelligent Platform Management Interface (IPMI) is an industry-standard environment that allows centralized monitoring and control of a computer system. The features of the IPMI support the management of CompactPCI or other systems containing multiple intelligent modules and other standard features such as sensors for system temperature, fan failure or chassis intrusion.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE 7.2 IPMI Compatibility This board implements a version of IPMI compatible with revision 1.5 of the IPMI specifications. It includes the mandatory elements of the PCI Industrial Computer Manufacturer’s Group (PICMG) specification 2.9. The IPMI facilities supported by the PP 41x/03x board are implemented using a microcontroller and its resident firmware with non-volatile operational data stored in EEPROM.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE 7.3 IPMI Overview The PP 41x/03x board includes hardware and firmware that implements an IPMI as a separate resource to the main Intel Pentium M processor. The processor communicates with the IPMI subsystem through a standardized hardware interface using multi-byte message sequences, transferring one byte at a time using a handshaking protocol. Instructions can be sent to the IPMI subsystem with a command and response message pair.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE 7.3.4 Sensors The PP 41x/03x board is capable of monitoring the temperature of the board and the processor chip, the levels of the main power supply voltage rails, the status of a system fan and the board’s Geographic Address (effectively its CompactPCI bus slot number). These sensors can be configured to generate events when, for example, the temperature of the processor chip exceeds a previously configured value.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE 7.4 Supported Commands The PP 41x/03x board supports a subset of the command messages as defined in the IPMI specification. All commands, unless explicitly stated, expect a response which is generally retrieved through the SMIC interface. Commands that are not supported receive a “Invalid Command” response. Table 7-1 list the commands supported by this board. Many of these commands are described in the IPMI specifications and no further details are provided here.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE IPM Device “Global” Commands BMC Watchdog Timer Commands BMC Device and Messaging Commands Chassis Device Commands Event Commands Sensor Device Commands FRU Device Commands SDR Device Commands SEL Device Commands NetFn CMD Get Device ID Broadcast Get Device ID Cold Reset Warm Reset Get Self Test Results Reset Watchdog Timer Set Watchdog Timer Get Watchdog Timer Set BMC Global Enables Get BMC Global Enables Clear Message Flags Get Message Flags Get Message
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE 7.4.1 Get Self Test Results Command On this board, no self test results are available via this command. The PC BIOS runs a Power On Self Test (POST) sequence, but the results of these tests are reported only via on-screen messages and flashes of the POST LED. The IPMI command always returns code 56h (meaning not supported). 7.4.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE 7.4.4 Sensor Commands The list of sensors fitted to this board, together with the sensor number and type information found in their SDRs, is provided in Table 7-2. These sensors are scanned by the IPMI subsystem at a rate of approximately 10 Hz. The values returned by the Get Sensor Reading command are the values obtained in the most recent scan.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE 7.4.4.1 Board and CPU Temperature Sensors An Analog Devices ADT7461 device measures the local board and CPU die temperature with a resolution of 0.125°C. The device has a quoted accuracy of +/- 1°C over a range of +60°C to +100°C, and of +/- 3°C outside this range. NOTE: A National Semiconductor LM86 device was fitted on Rev A and Rev B boards. The ADT7461 and LM86 are software compatible. 7.4.4.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE 7.4.4.10 Ejector Handle This sensor reading indicates the status of the ejector handle switch. If the value is 0, the handle is closed. If the value is 1, the handle is open. 7.4.4.11 Power Regulators Status This sensor indicates if the power regulators are working correctly. If they are, the sensor returns 1. Otherwise, if there is a problem, the sensor returns 0.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE 7.5 FRU Inventory Data The FRU Inventory Area shares the non-volatile memory with the repository of Sensor Data Records and the System Event Log and contains information about the board, including, for example, the manufacturer’s name, part number and serial number. The FRU Inventory Area comprises, at most, six information areas. Each area, if used, is always a multiple of 8 bytes in length.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE 7.5.2 Board Area The Board Area, in the FRU Inventory, contains information about the PP 41x/03x board. Its offset in the FRU Inventory Area is calculated by multiplying its offset value in the Common Header Area by 8. The Board Area is arranged as shown in Table 7-4.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE 7.6 Programming Examples 7.6.1 Using the SMIC Interface The PP 41x/03x board utilizes the Server Management Interface Controller (SMIC) as its interface with the I/O ports at the standard addresses (i.e. 0CA9h, 0CAAh and 0CABh). The IPMI specification has a complete description of the SMIC interface.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE /****************************************************************************** * * vBmcSmicSmsMessageWrite * * This function writes a SMS (System Managment Software) messages * to the IPMI using the standard BMC-SMIC interface.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE */ void vBmcSmicSmsMessageRead ( unsigned char *pbMessage, unsigned char *bMessageLength ) { unsigned char bReadControl; unsigned char bReadStatus; unsigned char bReadData; /* received response */ /* response length */ *bMessageLength = 0; bReadControl = CC_SMS_RD_START; do { while (((bReadSmicFlags) & FLAGS_RX_DATA_READY) != FLAGS_RX_DATA_READY) ; /* do nothing ... */ while (((bReadSmicFlags) & FLAGS_BUSY) == FLAGS_BUSY) ; /* do nothing ...
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE 7.6.2 Using the Watchdog Timer The IPMI provides a standardized watchdog facility which is fully described in the IPMI specification.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE /****************************************************************************** * * wSetWatchdog * * This function defines operation of the IPMI watchdog which is initiated * by the Reset Watchdog Command issued the the wResetWatchdog function.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE unsigned char bLength; unsigned short int wStatus = E_OK; abRequest [0] = NFC_APP_REQUEST << 2; abRequest [1] = CMD_WATCHDOG_RESET; /* command */ vBmcSmicSmsMessageWrite (abRequest, 2); vBmcSmicSmsMessageRead (abResponse, &bLength); if (abResponse [2] != COMPLETION_OK) wStatus = E_COMPLETION; return wStatus; } The following example shows how to set the watchdog to power cycle if the watchdog is not restarted within 20 seconds, generate an NMI if there is less than
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE 7.6.3 Reading Sensors The IPMI specification supports many commands to manage and interrogate sensors. The following program fragment illustrates how the current reading of a sensor can be obtained.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE unsigned char abRequest [10]; unsigned char abResponse [10]; unsigned short int wStatus = E_OK; /* Send Request */ abRequest [0] = NFC_SENSOR_EVENT_RQ << 2; abRequest [1] = CMD_GET_SENS_RD; /* command */ abRequest [2] = bSensorId; vBmcSmicSmsMessageWrite (abRequest, 3); vBmcSmicSmsMessageRead (abResponse, &bLength); if (abResponse [2] != COMPLETION_OK) wStatus = E_COMPLETION; else { psSensorReading->bData = abResponse [3]; psSensorReading->bStatus = abResponse [4];
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE 7.7 In System Programming The PP 41x/03x allows the IPMI microcontroller firmware to be updated in-system. The firmware mode switch enables this feature. This switch is shown in Figure 7-1 below. NOTE: The Firmware Mode switch should normally be set in the Normal (OFF) position. Contact your local distributor or Concurrent Technologies directly if you need to update the IPMI microcontroller firmware.
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INTELLIGENT PLATFORM MANAGEMENT INTERFACE This page has been left intentionally blank 7-22 PP 41x/03x
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8 8.1 FLASH EPROM AND DRAM Flash EPROM The PP 41x/03x is fitted with one Flash EPROM part, namely an Intel 82802AC8 or equivalent Firmware Hub (FWH). This device is soldered to the board and is programmed at the factory with PC BIOS and factory test firmware. This EPROM will not normally be reprogrammed by the user, but Concurrent Technologies has programming software which allows BIOS updates to be carried out in the field when necessary, perhaps to add new features.
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FLASH EPROM AND DRAM This page has been left intentionally blank 8-2 PP 41x/03x
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9 ADDITIONAL LOCAL I/O FUNCTIONS The PP 41x/03x supports a variety of I/O functions whose addresses are summarized in Table 9-1. NOTE: An LPC Super I/O controller (designated TM Super I/O in Table 9-1) is located on the AD PP5/001-4xU Transition Module. This device provides some of the legacy peripheral functions.
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ADDITIONAL LOCAL IO FUNCTIONS Most of the addresses are standard PC-AT compatible values, but at addresses 0210h - 021Fh and 0CA9h – 0CABh the board provides custom Status and Control registers for the board specific features. There are 13 byte wide Status and Control registers. They fall into four groups, namely, generalpurpose registers, temperature sensor data registers, ACPI registers and IPMI SMIC interface registers.
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ADDITIONAL LOCAL IO FUNCTIONS 9.1 Status & Control Register 0 This register is at I/O address 210h. 7 6 5 4 3 2 1 0 REV2 REV1 REV0 RFU CONSOLE PORT CONSOLE USER MODE Bit 0: Mode Switch (Read Only) Used to define the operating mode following a reset. 0 = BIOS operation 1 = CPSA operation Bit 1: User Switch (Read Only) Bit 1: User Switch (Read Only) Available for user defined purposes when the board starts up in BIOS mode (see Section 10.1).
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ADDITIONAL LOCAL IO FUNCTIONS 9.2 Status & Control Register 1 This register is at I/O address 211h. 7 6 5 4 3 2 1 0 FP NMI IPMI NMI DEG & FAL NMI MASK GPE# STATUS GPE# SMI ENABLE PME# STATUS PME# SMI ENABLE USER LED Bit 0: User LED (Read/Write) 0 = User LED Off 1 = User LED On NOTE: The User LED may be configured to light when the CPU reaches its maximum specified operating temperature (see Section 11.2.3). In this configuration, writing to this bit will not affect the User LED.
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ADDITIONAL LOCAL IO FUNCTIONS 9.3 Status & Control Register 2 This register is at I/O address 212h.
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ADDITIONAL LOCAL IO FUNCTIONS 9.4 General Purpose I/O Register This register is at I/O address 213h.
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ADDITIONAL LOCAL IO FUNCTIONS 9.5 CPCI Status Register This register is at I/O address 214h. 7 6 5 4 3 2 1 0 RFU FAL# DEG# CPCI V(I/O) OK CPCI BUS SPEED FORCE SATELLITE PCI PRESENT SYSEN# Bit 0: CompactPCI SYSEN# Pin Status (Read Only) This bit indicates whether or not the board is plugged into the System Controller slot.
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ADDITIONAL LOCAL IO FUNCTIONS 9.6 Interrupt Control Register This register is at I/O address 215h. It provides control over interrupts from the IPMI. 7 6 5 4 3 2 1 0 ISP MODE GPI INT FLAG SMS_ATN INT FLAG SMIC NOT BUSY INT FLAG RFU GPI INT ENA SMS_ATN INT ENA SMIC NOT BUSY INT ENA Bit 0: SMIC Not Busy Interrupt Enable (Read/Write) This bit allows an interrupt to be generated when the IPMI microcontroller clears the SMIC BUSY flag.
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ADDITIONAL LOCAL IO FUNCTIONS 9.7 Temperature Sensor Data Register This register provides a convenient means of reading the analog temperature sensor on the processor chip. Data is posted in this register at regular intervals by the IPMI sub-system. Further details are beyond the scope of this document. User software should treat this register as read-only and should not attempt to write to it. 9.7.1 Analogue Temperature Sensor Data Register This register is at I/O address 216h.
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ADDITIONAL LOCAL IO FUNCTIONS 9.8 ACPI PM1 Control Register This 16-bit register is located at I/O addresses 21Eh and 21Fh. It provides a minimal power management interface. Further details are beyond the scope of this document. User software should not access these locations.
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ADDITIONAL LOCAL IO FUNCTIONS 9.9 Interrupt Configuration Register This register is at I/O address 21Dh. 7 6 5 4 3 2 1 0 IPMI INTERRUPT STATUS PIT INTERRUPT STATUS PIT INTERRUPT ENABLE M66EN INTERRUPT FLAG M66EN INTERRUPT ENABLE ENUM# STATUS ENUM# INTERRUPT ENABLE ENUM# ROUTING Bit 0: CompactPCI ENUM# Interrupt Routing (Read/Write) This bit selects which interrupt the CompactPCI ENUM# signal is routed to. This interrupt is only relevant when the board is System Controller.
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ADDITIONAL LOCAL IO FUNCTIONS 9.10 IPMI SMIC Interface The IPMI sub-system is accessed by the local CPU using the SMIC interface (see Chapter 7 for an explanation of these terms and of the purpose of IPMI). The following sections outline the register contents, and example code for using this interface is provided in Section 7.6. 9.10.1 SMIC Data Register This register is at I/O address 0CA9h. It is dual-ported. Both the CPU and the IPMI microcontroller can read it or write to it.
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ADDITIONAL LOCAL IO FUNCTIONS 9.11 P.O.S.T. LED / Speaker The P.O.S.T. LED is controlled via the speaker port. The P.O.S.T. LED replaces a PC speaker and is programmed in the same way a speaker would be programmed. The board also outputs the speaker port via a high current open collector driver on the CompactPCI J5 connector for connection to an external speaker if required.
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ADDITIONAL LOCAL IO FUNCTIONS 9.12 PORT 80 A header (S1 – see Figure A-1) has been provided for monitoring data written to I/O Port 80 and I/O Port 81. The PC BIOS writes status bytes to Port 80 that indicate a boot progress status and/or highlight any faults found. Data written to this port can be monitored using a Logic State Analyzer (LSA) or seven segment hexadecimal displays. See Section A.5.9 for details of the connector used for this port. The PC BIOS also writes status information to Port 81.
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10 PC BIOS The PP 41x/03x board is fitted with PC BIOS firmware that performs many of the functions of a standard desktop PC. It also includes additional features specifically tailored for the CompactPCI bus environment. In addition to the core BIOS firmware, the board is fitted with BIOS Extensions for remote boot-load capability via any of the on-board Ethernet channels.
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PC BIOS Operator communication with the PC BIOS is usually through a serial terminal connected to the COM1 or COM2 serial ports. This can be reconfigured with a board option switch to use a VGA display (either using the on-board graphics interface, if fitted, or via a PMC module) and a separate keyboard. Section 6.1.1 describes the location and settings for this switch. Selection between COM1 and COM2 is done via a board option switch. Section 6.1.2 describes the location and settings for this switch.
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PC BIOS 10.2 The PC BIOS Startup Sequence When the board starts up without operator intervention, it will run a basic Power-On Self-Test (POST) sequence, including ECC DRAM initialization and a DRAM test. The full DRAM test will be omitted on subsequent restarts if the BIOS configuration settings have not been changed. Once the DRAM test has completed, the board will try to boot-load application software from any attached mass storage medium or through one or both of the Ethernet interfaces.
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PC BIOS 10.3 Boot Device Selection The order in which the PC BIOS searches for a bootable medium is pre-configured but may be altered by the operator using the Boot setup menu. When the order is changed using this menu it will be retained in non-volatile memory so that the order is maintained after a restart. It is also possible to specify a one-time override of the boot device when the board starts, by pressing the key. This will result in a pop-up menu appearing.
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PC BIOS 10.4 PCI Bus Resource Management The bus structure of the PP 41x/03x is complex. There are three on-board PCI busses, namely: • A 32-bit bus which connects the 6300ESB ICH to the SM722 graphics controller. • A 64-bit bus which connects the 6300ESB ICH to PMC Site 1. • A 64-bit bus which connects the PEX8114 PCI Express to PCI-X bridge to PMC Site 2 and the PCI6540 CompactPCI bridge. The 32-bit bus operates at 33 MHz with 3.3V signaling levels. The 64-bit bus to PMC Site 1 operates with 3.
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PC BIOS The interrupt controller in the 6300ESB ICH can operate in two basic modes, namely PIC (or NonAPIC) mode and APIC mode. PIC mode corresponds to the legacy PC interrupt structure. APIC mode provides additional interrupts and several functional improvements. Table 10-1 lists the allocation of the various PCI and PCI Express devices to interrupt inputs on the 6300ESB ICH. These allocations are fixed and cannot be changed by the user.
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PC BIOS Table 10-3 lists the typical interrupt structure in APIC mode. A total of 24 interrupts are available. The 6300ESB ICH interrupt inputs PIRQA – PIRQH are mapped to IRQ16 – IRQ23 respectively.
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PC BIOS 10.4.3 PCI Device IDs Each PCI bus, and each device on an individual PCI bus, has a unique ID. For the PP 41x/03x, the bus and device IDs are listed in Table 10-2. The PCI bus numbers in this table assume that the board is fitted into the System Controller slot, that no PMC or XMC modules are fitted and that no bridges are present on the CompactPCI bus. If the board is fitted into a Peripheral slot, then the CompactPCI bus will not be visible and subsequent bus numbers will be one lower (e.g.
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PC BIOS 10.4.4 CompactPCI Bridge Configuration The BIOS provides Setup menus that allow configuration of certain features of the CompactPCI Bridge, these can be found under the CompactPCI top level menu. The fields available via Setup depend on the board’s operating mode. 10.4.5 System Controller Mode In System controller mode two Setup options are provided: ENUM Interrupt allows the user to specify whether the CompactPCI ENUM interrupt drives NMI or IRQ5.
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PC BIOS 10.4.8 Peripheral Mode Window-Size Limitations The CompactPCI bridge forms PCI addresses by concatenating the least significant bits from the CPU generated address and the most significant bits from the translation base address; the contribution from each part is fixed and depends upon the window type. However, the BIOS always aligns base addresses according to their resource size, to achieve optimal packing.
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PC BIOS 10.5 User Selectable NVRAM Defaults The BIOS provides a facility through which the user can save preferred setup option settings to Flash memory (NVRAM). Then, if the BIOS detects that the contents of NVRAM is corrupt, the user can elect to restore the contents from the saved settings, rather than loading factory configured defaults. This facility also allows the board to operate without fitting the battery, but with NVRAM settings different to the factory defaults.
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PC BIOS 10.6 The Recovery BIOS In the unlikely event that the board’s BIOS ROM contents becomes corrupted and it is not possible to perform the normal BIOS update procedure, the board provides a minimal Recovery BIOS that will allow the board to boot from a specially prepared floppy disk and restore a known-good BIOS image. The Recovery BIOS is located in a special sector in the BIOS ROM that is protected from accidental erasure by hardware means.
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11 SYSTEM MANAGEMENT 11.1 Power Management The Intel Core Duo processor incorporates a mechanism for changing the processor’s operating frequency and core voltage under software control. By making these reductions the board’s maximum power consumption is also reduced substantially. The Intel Core Duo processor supports a number of discrete operating frequencies that vary between 1.0 GHz and full speed (see Table 11-1).
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SYSTEM MANAGEMENT 11.2 Thermal Management The maximum power dissipation of the Intel Core Duo processor may sometimes be higher than that of previous Intel Pentium M processors. Under typical load conditions, the heatsink (and cooling airflow) will keep the processor die temperature within specification. However, if the board is running CPU-intensive or stress software or if the airflow is inadequate, the heatsink alone may not be able to prevent the processor overheating.
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SYSTEM MANAGEMENT 11.2.4 PC BIOS Setup Options The PC BIOS Setup Menu provides control over the thermal management functions, using the setting for the Advanced | Advanced Processor Options | Thermal Control Circuit option.
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SYSTEM MANAGEMENT 11.3 ECC Error Logging The E7520 MCH includes hardware for detecting and correcting single-bit ECC errors and for detecting multi-bit ECC errors. Both types of ECC error can be recorded by the BIOS via the DMI Event Log (Advanced | DMI Event Logging | View DMI event log). 11.3.1 Single-bit ECC Errors Single-bit ECC errors are a rare occurrence in normal operation. The chipset will detect single bit errors during memory reads and automatically pass the corrected data to the CPU instead.
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A A.1 SPECIFICATIONS Functional Specification Processor: • Level 1 Caches: Level 2 Cache: • • Memory: • • Interfaces: • • • • • • • • • • • • • • • Peripherals: • • • PP 41x/03x 2.0 GHz or 1.66 GHz Intel Core Duo processor or 2.16 GHz Intel Core 2 Duo processor. 32Kbytes instruction cache and 32 Kbytes data cache. 2048 Kbytes (Core Duo) or 4096 Kbytes (Core 2 Duo) on-die RAM operating at core frequency. 1 Mbyte Flash EPROM for PC BIOS using soldered 82802AC8 or equivalent Firmware Hub device.
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SPECIFICATIONS A.2 Environmental Specification (N Series) A.2.1 Temperature Range Operating................... 0ºC to +55ºC @ 400LFM air flow Storage...................... -40ºC to +85ºC The processor die temperature can be monitored via the IPMI subsystem (see Section 7.4.4) or by reading various status registers (see Section 9.7).
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SPECIFICATIONS A.3 Dimensions Height ........................ Depth......................... Width ......................... Weight ....................... 23.3cm 16.0cm 2.0cm 800g (2.0 GHz / 2.16GHz variants) 660g (1.66 GHz variants) NOTE: The above weights are for a board with 1 Gbyte DDR2 memory and two PMC covers fitted and no PMC module(s) or Mass Storage Kit or CompactFlash module fitted.
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SPECIFICATIONS A.4 Electrical Specification A.4.1 Power Supply Requirements Full Speed Actual Speed 2.16 GHz 2.16 GHz 1.66 GHz 1.33 GHz 1.0 GHz 2.0 GHz 2.0 GHz 1.66 GHz 1.0 GHz 6.2A 5.3A 3.9A 9.5A 7.5A 4.4A 3.8A 3.8A 3.8A 1.66 GHz 1.66 GHz 1.33 GHz 1.0 GHz 4.8A 4.4A 4.0A 6.7A 5.7A 4.9A 3.4A 3.4A 3.4A Table A-1 +5V +5%, -3% Typical Maximum 6.4A 11.4A 5.2A 8.5A 4.6A 7.2A 4.1A 5.9A +3.3V +5%, -3% Typical Maximum 3.5A 4.4A 3.5A 4.4A 3.5A 4.4A 3.4A 4.4A +12V +/-5% Maximum 0.05A 0.05A 0.05A 0.
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SPECIFICATIONS A.
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SPECIFICATIONS A.5.1 CompactPCI Interface (J1) Pin-outs The CompactPCI interface connector J1 consists of a 150-pin connector with pins assigned as follows: Pin 25 24 23 22 21 20 19 18 17 16 15 12-14 11 10 9 8 7 6 5 4 3 2 1 Pin A 5V AD[1] 3.3V AD[7] 3.3V AD[12] 3.3V SERR# 3.3V DEVSEL# 3.
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SPECIFICATIONS A.5.
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SPECIFICATIONS A.5.3 CompactPCI Interface (J3) Pin-outs The CompactPCI interface I/O connector J3 consists of a 114-pin connector with pins assigned as follows: Pin 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Pin A GND LPa_DA LPa_DB LPb_DA LPb_DB +3.3V I/O 5 I/O 10 I/O 15 I/O 20 I/O 25 I/O 30 I/O 35 I/O 40 I/O 45 I/O 50 I/O 55 I/O 60 SPKR Out A B GND LPa_DA# LPa_DB# LPb_DA# LPb_DB# +3.
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SPECIFICATIONS A.5.4 CompactPCI Interface (J5) Pin-outs The CompactPCI interface I/O connector J5 consists of a 132-pin connector with pins assigned as follows.
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SPECIFICATIONS A.5.5 On-Board Mass Storage Option Connector (P5) Pin-outs Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 Table A-6 A-10 Signal Name IDE_RST# SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0 GND SDREQ SDIOW# SDIOR# SIORDY SDDACK# INT15# SDA1 SDA0 SDCS1# ACTIVITY# +5V GND Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 Signal Name GND SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 +3.
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SPECIFICATIONS A.5.6 PMC Site Connectors (J11 - J14 and J21 - J24) Pin-outs Signal assignments on the PMC connectors are shown in Tables A-7, A-8, A-9 and A-10. Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Signal Name NC GND INTB# BUSMODE#1 INTD# GND CLK GND REQ# V (I/O) AD(28) AD(25) GND AD(22) AD(19) V (I/O) FRAME# GND DEVSEL# GND SDONE#† PAR V (I/O) AD(12) AD(09) GND AD(06) AD(04) V (I/O) AD(02) AD(00) GND Pin No.
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SPECIFICATIONS Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Signal Name +12V NC NC GND NC +3.3V†† RST# +3.3V NC AD(30) GND AD(24) IDSEL +3.3V AD(18) AD(16) GND TRDY# GND PERR# +3.3V C/BE(1)# AD(14) M66EN AD(08) AD(07) +3.3V PMC-RSVD PMC-RSVD GND ACK64# GND Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 Signal Name NC NC GND NC NC +3.3V GND GND GND AD(29) AD(26) +3.
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SPECIFICATIONS Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Signal Name NC GND C/BE(6)# C/BE(4)# V(I/O) AD(63) AD(61) GND AD(59) AD(57) V(I/O) AD(55) AD(53) GND AD(51) AD(49) GND AD(47) AD(45) V(I/O) AD(43) AD(41) GND AD(39) AD(37) GND AD(35) AD(33) V(I/O) NC NC GND Pin No.
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SPECIFICATIONS Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Table A-10 A-14 Signal Name I/O 1 I/O 3 I/O 5 I/O 7 I/O 9 I/O 11 I/O 13 I/O 15 I/O 17 I/O 19 I/O 21 I/O 23 I/O 25 I/O 27 I/O 29 I/O 31 I/O 33 I/O 35 I/O 37 I/O 39 I/O 41 I/O 43 I/O 45 I/O 47 I/O 49 I/O 51 I/O 53 I/O 55 I/O 57 I/O 59 I/O 61 I/O 63 Pin No.
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SPECIFICATIONS A.5.7 XMC Connector (J25) Pin-out PMC Site 2 is also equipped with an XMC interface connector. The pin-out of this connector is shown below. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Row A PET0p0 GND PET0p2 GND PET0p4 GND PET0p6 GND NC GND PER0p0 GND PER0p2 GND PER0p4 GND PER0p6 GND REFCLK+ Row B PET0n0 GND PET0n2 GND PET0n4 GND PET0n6 GND NC GND PER0n0 GND PER0n2 GND PER0n4 GND PER0n6 GND REFCLK- Table A-11 Row C +3.3V PULL DOWN +3.3V PULL DOWN +3.3V PULL UP +3.
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SPECIFICATIONS A.5.8 Ethernet Connector (P2) Pin-out The front panel Ethernet Interface uses an 8-way RJ45 connector with the following pin-out: Pin No.
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SPECIFICATIONS A.5.9 Port 80 (S1) Pin-outs Port 80 may be used for debugging purposes and the pin-out for the connector that provides its output signals is shown below. The connector also includes a Port 81 select signal as the BIOS writes status information to that port (see Section 9.12). Pin No.
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SPECIFICATIONS A.5.10 Shared Front Panel Connector (J6) Pin-outs This connector provides access to the keyboard, mouse, VGA video, COM1 serial port and USB0 port interfaces. It is a female high-density 26-way D-type connector. The pin-out is as follows. Figure A-3 Pin No. 26 25 24 23 22 21 20 19 Signal Name KBD/Mouse VCC GND USBD0 USBD0# DDC Clock VSYNC HSYNC DDC Data Table A-14 Shared Front Panel Connector Layout Pin No.