User Guide

Hardware and Software Design • Manufacturing Services
P a g e 9
The serial channels are each supported by a 128 by 32-bit FIFO. The FIFOs
support long word reads and writes. A full 32-bit path exists for loop-back testing
of each FIFO. Data is latched and the bus immediately released on a write-cycle.
On a read cycle the data is read after the bus is released from the previous read.
This has the effect of adding one extra read to start capturing data, but means
there is no delay in future reads.
The serial format for transmit and receive is 32 bits per word, LSB first. The
data switches on the falling edge of the reference clock and is valid on the rising
edge. The strobe is asserted on the falling edge before the first data bit should
be taken and held on until the falling edge after the last bit. If more than one
word is sent the words are sent back-to-back without a gap.
The transmit data is sent with the clock and strobe. If the receiver operates as
an asynchronous interface then the first data word can be a sync pattern and the
clock and strobe ignored. The receiver on the PS2 utilizes the clock and the
strobe. The clock is free-running.
The serial receive channels can receive continuous or burst data. The host can
poll the FIFO flags or wait for the programmable FIFO interrupt. The message can
then be read over the PCI bus directly from the FIFO.
The Output channels have a separate 128 x 32-bit FIFO each. The FIFO is written
as long words. Normal operation is to load the TX FIFO for the channel of
interest then set the TX Start bit. The data will start to be transmitted at the
programmed rate along with the strobe. The clock will already be running. The
state-machine will continue to read data from the FIFO and transmit until the FIFO
is empty. When the transmission is completed a programmable interrupt can be
set. The start bit is automatically cleared at the end of a transmission.
Various interrupts are supported by the PMC BiSerial-II PS2. An interrupt can be
configured to occur at the end of a transmitted message. An interrupt can be set
at the end of a reception. Interrupts can occur based on the IO. All interrupts are
individually maskable and a master interrupt enable is also provided to disable all
interrupts simultaneously. The current status is available for the FIFOs making it
possible to operate in a polled mode.