User Guide

Hardware and Software Design • Manufacturing Services
P a g e 7
The standard configuration shown in Figure one makes use of two external [to the
Xilinx ] FIFOs. The FIFOs can be as large as 128K deep x 32 bits wide. Some
designs do not require so much memory and are more efficiently implemented
using the internal FIFOs.
FIGURE 2 PMC BISERIAL-II PS2 BLOCK DIAGRAM
The PS2 implementation has 8 - 128 x 32 FIFOs using the internal block RAM of
the Xilinx. Each TX and RX channel has an associated FIFO. The transmit FIFOs
have the option to fill in parallel - if the same data pattern is to be sent from the 4
485 buffers
termination
PCI IF
FIFO RX
128 x 32
FIFO TX
128 x 32
State
Machine
RX
State
Machine
TX
Data Flow
Control
x4
x4
x4
x4
Parallel Port
8 IO
COS Int