User Guide

Hardware and Software Design • Manufacturing Services
P a g e 5
List of Figures
FIGURE 1 PMC BISERIAL-II BLOCK DIAGRAM 6
FIGURE 2 PMC BISERIAL-II PS2 BLOCK DIAGRAM 7
FIGURE 3 PS2 TIMING DIAGRAM 11
FIGURE 4 PMC BISERIAL-II PS2 INTERNAL ADDRESS MAP 13
FIGURE 5 PMC BISERIAL-II BASE CONTROL REGISTER BIT MAP 15
FIGURE 6 PMC BISERIAL-II INTERRUPT ENABLE REGISTER BIT MAP 16
FIGURE 7 PMC BISERIAL-II TX CONTROL REGISTER BIT MAP 17
FIGURE 8 PMC BISERIAL-II RX CONTROL REGISTER BIT MAP 18
FIGURE 9 PMC BISERIAL-II PARALLEL OUTPUT DATA BIT MAP 19
FIGURE 10 PMC BISERIAL-II STATUS REG 0 BIT MAP 20
FIGURE 11 PMC BISERIAL-II STATUS 1 BIT MAP 22
FIGURE 12 PMC BISERIAL-II COSEN REGISTER BIT MAP 24
FIGURE 13 PMC BISERIAL-II DIRECTION TERMINATION CONTROL BIT MAP 26
FIGURE 14 PMC BISERIAL-II COSEDGE REGISTER BIT MAP 28
FIGURE 15 PMC BISERIAL-II PN1 INTERFACE 31
FIGURE 16 PMC BISERIAL-II PN2 INTERFACE 32
FIGURE 17 PMC BISERIAL-II FRONT PANEL INTERFACE 33