User Guide

Hardware and Software Design • Manufacturing Services
P a g e 29
Interrupts
PMC BiSerial-II interrupts are treated as auto-vectored. When the software
enters into an exception handler to deal with a PMC BiSerial-II interrupt the
software must read the status register to determine the cause(s) of the interrupt,
clear the interrupt request(s) and process accordingly. Power on initialization will
provide a cleared interrupt request and interrupts disabled.
For example, the PMC BiSerial-II Tx state machine generates an interrupt request
when a transmission is complete and the Tx int enable and Master interrupt
enable bits are set. The transmission is considered complete when the last bit is
output from the output shift register.
The interrupt is mapped to INTA on the PMC connector, which is mapped to a
system interrupt when the PCI bus configures. The source of the interrupt is
obtained by reading BIS2_STAT0. The status remains valid until that bit in the
status register is explicitly cleared.
When an interrupt occurs, the Master interrupt enable should be cleared and the
status register read to determine the cause of the interrupt. Next perform any
processing needed to remove the interrupting condition, clear the latched bit and
set the Master interrupt enable bit high again.
The individual enables operate after the interrupt holding latches, which store the
interrupt conditions for the CPU. This allows for operating in polled mode simply
by monitoring the BIS2_STAT0 register. Alternatively, the conditions of interest
can be enabled, but the Master interrupt enable left disabled. Then the interrupt
status bit in BIS2_STAT0 can be monitored. If one of the enabled conditions
occurs, the interrupt status bit will be set, but unless the Master interrupt enable
is set, a system interrupt will not occur.