User Guide

Hardware and Software Design • Manufacturing Services
P a g e 25
BIS2_FIFOTX0-3
[$28,2C,30,34] BiSerial II Tx FIFO write-read port
The BiSerial II supports 32-bit writes to the transmit data FIFO. Data is aligned
D31-0. Normally this port is only written to, but for loop-back testing the contents
of the FIFO can be read out over the PCI bus. The data is moved from the FIFO to
the holding register at the end of a read cycle. The first read will return whatever
is in the holding register, the second will return the first data… The engineering
kit contains software, which performs a Tx FIFO loop-back test on each channel.
Once data is read from the FIFO it is no longer available for transmission. There
is a bit in the BIS2_TX register which causes the data written to channel 0 to also
be written to channels 1,2, and 3. If the same data is to be transmitted out of
each port this feature can save 3 FIFO fill operations.
BIS2_FIFORX0-3
[$20,24,3C,40] BiSerial II Rx FIFO write-read port
The BiSerial II supports 32-bit reads from the receive data FIFO. Data is aligned
D31-0. Normally this port is only read from, but for loop-back testing the contents
of the FIFO can be written from the PCI bus. The FIFO loop back bit in the Rx
control register must be set to a '1' in order to accomplish this. The engineering
kit contains software, which performs an Rx FIFO loop-back test. Once data is
read from the FIFO it is no longer available.
The data path from the FIFO to the host is pipelined through a holding register.
After reset or a condition where the last read of the FIFO holding register
happened with an empty FIFO a pre-read will be required to move data from the
FIFO to the holding register. In most cases, with messages completely stored
within the FIFO, this will equate to one pre-read followed by the message count
reads to retrieve the stored message.