User Guide

Hardware and Software Design • Manufacturing Services
P a g e 24
BIS2_COSEN
[$1C] BiSerial II Parallel Enable COS register
Parallel Enable Change of State Register
DATA BIT DESCRIPTION
31-24 spare
23-16 par_int_en_f
15-8 par_int_en_r
7-0 par_en7-0
FIGURE 12 PMC BISERIAL-II COSEN REGISTER BIT MAP
Par_en bits 7-0 correspond to the parallel IO port bits. When set the COS
function is enabled for that input bit. Normally the par_en bit will not be enabled
for ports defined to be outputs. Once enabled, the state-machine will continue to
process COS until disabled by setting to '0'. The state-machine will return to the
idle state and wait to be enabled again. Disabling the COS detector will not affect
previously captured status in Stat0. That will have to be cleared explicitly.
Par_int_en_r bits 7-0 correspond to the parallel IO port bits. If the par_en is set
and a rising edge is detected for the IO line(s) enabled then the interrupt is
triggered to the host. The master enable is also required. The corresponding
Rising bit must also be set. The status register [Stat0] will capture the event
even if the interrupt is not enabled to allow polled operation.
Par_int_en_f bits 7-0 correspond to the parallel IO port bits. If the par_en is set
and a falling edge is detected for the IO line(s) enabled then the interrupt is
triggered to the host. The master enable is also required. The corresponding
Falling bit must also be set. The status register [Stat0] will capture the event
even if the interrupt is not enabled to allow polled operation.