User Guide

Hardware and Software Design • Manufacturing Services
P a g e 21
The interrupt conditions are latched and held in special interrupt status latches.
The latched signals are made available on the Bis2_stat0 port. The latched bits
remain set until the corresponding bit is written back to the port. When an
interrupt occurs or if polling is used this port can be used to determine which
channel requires attention. The active channel should be taken care of and then
the bit set to clear the request. The combination of port access and bit position
set is used to clear the bit. No second write is required to re-enable the latching
mechanism.
Tx0-3_intr_lat is set when the transmitter completes a transfer. To use as an
interrupt the Tx_Int_En0-3 [Bis2_TX] must also be set as well as the master
interrupt enable.
Rx0-3_intr_lat is set when the receiver completes a reception. To use as an
interrupt the Rx_Int_En0-3 [Bis2_RX] must also be set as well as the master
interrupt enable.
R0-7_intr_lat is set when the parallel port bit has received a rising transition
0->1. To use as an interrupt the par_int_en_r0-7 [Bis2_COSEN] must also be set
as well as the master interrupt enable.
F0-7_intr_lat is set when the parallel port bit has received a falling transition
1->0. To use as an interrupt the par_int_en_f0-7 [Bis2_COSEN] must also be set
as well as the master interrupt enable.