User Guide

Hardware and Software Design • Manufacturing Services
P a g e 18
BIS2_RX
[$0C] BiSerial II Rx Control Register Port read/write
CONTROL RX
DATA BIT DESCRIPTION
31-12 Spare
11 loop_back3
10 loop_back2
9 loop_back1
8 loop_back0
7 int_en_rx3
6 int_en_rx2
5 int_en_rx1
4 int_en_rx0
3 start_rx3
2 start_rx2
1 start_rx1
0 start_rx0
FIGURE 8 PMC BISERIAL-II RX CONTROL REGISTER BIT MAP
Start_rx0-3 when '1' enables the receiver state machine to receive messages. If
Start_rx0-3 is set to a zero the reception will stop after the current word is
stored in the FIFO. Start_rx0-3 is auto-cleared at the end of a reception.
Int_en_rx0-3 when '1' the interrupt for the corresponding channel will be asserted
at the completion of a reception. The master interrupt enable is also required to
be enabled. Please note that the channel status can be read without using
interrupts.
Loop-back0-3 when '1' enables the receiver FIFO for that channel to be loaded
from the PCI bus instead of the receiver state-machine. Loop-back testing can be
accomplished with the FIFOs.