User Guide

Hardware and Software Design • Manufacturing Services
P a g e 16
BIS2_TX
[$04] BiSerial II Transmitter Register Port read/write
CONTROL INTERRUPT ENABLE
DATA BIT DESCRIPTION
31-11 Spare
10 tx load control
9 tx clock control
8 spare
7 int_en_tx3
6 int_en_tx2
5 int_en_tx1
4 int_en_tx0
3 start_tx3
2 start_tx2
1 start_tx1
0 start_tx0
FIGURE 6 PMC BISERIAL-II INTERRUPT ENABLE REGISTER BIT MAP
All bits are active high and are reset on power-up or reset command.
Start_tx0 - 3 when '1' and data is loaded into the corresponding FIFO causes the
transmitter state-machine to begin a data transfer. When the transfer is
complete this bit is auto-cleared. The transmission length is controlled by the
amount of data stored into the FIFO.
Int_en_tx0-3 when '1' the interrupt for the corresponding channel will be asserted
at the completion of a transmission. The master interrupt enable is also required
to be enabled. Please note that the channel status can be read without using
interrupts.
Tx clock control when '1' enables the clocks associated with the transmit
channels to be driven. If the clocks are not used then this bit can remain in the
'0' state. Some interfaces treat the data asynchronously and do not use the
reference clock.