User Guide

Hardware and Software Design • Manufacturing Services
P a g e 15
Register Definitions
BIS2_BASE
[$00] BiSerial II Base Control Register Port read/write
CONTROL BASE
DATA BIT DESCRIPTION
31-9 Spare
8 Reset FIFO RX
7-5 spare
4 Reset FIFO TX
3 spare
2 spare
1 Interrupt Set
0 Interrupt Enable Master
FIGURE 5 PMC BISERIAL-II BASE CONTROL REGISTER BIT MAP
All bits are active high and are reset on power-up or reset command.
Interrupt Enable Master when '1' allows interrupts generated by the
PMC-BiSerial-II-PS2 to be driven onto the backplane [INTA]. When '0' the
interrupts can be individually enabled and used for status without driving the
backplane. Polled operation can be performed in this mode.
Interrupt Set when '1' and the Master is enabled, forces an interrupt request.
This feature is useful for testing and software development.