Specifications

46 158004.B00
The PCI bus interrupts are active-low level-sensitive interrupts. In principle, several
cards can drive the same INTx# pin low, and one board may drive more than one
interrupt line. In practice, few boards drive more than one INTx# line, and a rotation of
the INTx# pins from one slot to the next ensures that if each of four boards drive their
INTA# pin, the TP400 will see one interrupt on each of INTA#, INTB#, INTC# and
INTD#.
Table 8 lists the interrupt pin allocation for each PC/104-Plus slot.
The on-board Ethernet chip is normally configured as INTD#, although a solder link
option allows it to be set as INTA# (see Appendix B for configuration information).
The internal USB controller within the Geode GX1 chip set is treated as though it
were a PCI bus peripheral. It is connected (internally) to the INTA# line. Its interrupt
can also be allocated by the BIOS Setup program (see section 4.5.3 below).
If the USB controller is being used then it is not possible to install a PC/104-Plus card
that will generate interrupts in the Slot 1 position. This is because both the USB
controller and the Slot 1 PC/104-Plus card will attempt to drive the INTA# line.
(Current versions of the BIOS do not support any card in Slot 1, but later BIOSes may
allow a card so long as it does not conflict with a USB controller interrupt).
When a PCI device (which includes the on-board USB controller and Ethernet chip) is
detected by the BIOS during the power-on self test (POST) process, the BIOS
allocates an IRQ level to it, from what the BIOS understands to be the pool of
unallocated interrupts. It is possible to use a BIOS Setup menu option to influence
this allocation. This is discussed in section 4.5.3 below.
The Geode GX1 does not have a dedicated NMI pin, so non-maskable interrupts are
not available on the TP400’s PC/104 bus. The SERR# and PERR# pins however may
generate non-maskable interrupts, which are emulated by SMI code.
4.5.3 Plug and Play Control of Interrupts
The PnP BIOS is aware of most of the interrupt requirements of the on-board
peripherals. It uses this information to try to eliminate conflicts between different
devices requiring the same IRQ. This is most evident with PCI bus devices, which
normally have their IRQ level allocated to them by the PnP BIOS during power-on self
test (POST). The PnP BIOS allocates an IRQ level that is believes is unused.
This gives rise to a few anomalies. Firstly, the PnP BIOS is not aware of the
existence of COM3 or COM4. It is therefore possible for their interrupts (IRQ5 or
IRQ9) to be allocated to other PnP devices (internal devices or PCI boards) without
the PnP BIOS being aware of a conflict. Secondly, the PnP BIOS thinks that the
COM1, COM2 and printer ports always require their interrupts (IRQ4, IRQ3 or IRQ7),
and will not allocate these to other devices, or will flag a conflict if these interrupts are
allocated manually.
The BIOS Setup program allows a considerable degree of manual control over the
allocation of interrupts. This can overcome the PnP anomalies referred to above. The
Advanced / PCI Configuration / ISA Resource Exclusion menu allow interrupts to be
reserved for COM3 and COM4 if required. The Advanced / PCI Configuration / USB
IRQ and / PCI IRQ menus allow specific interrupts to be allocated to the USB and