Specifications

158004.B00 E9
E.7 FLAT PANEL CONNECTOR
The flat panel display is connected through J8, a straight 0.05” pitch 40-way pin
header. Pin assignments are shown in Table E11. Table E12 describes the functions
of the signals.
The LCD panel signal names and may vary from panel to panel, however the signal
descriptions should remain virtually the same. Use Tables E11 and E12 to help you
create an interface cable to connect between the TP400 and your flat panel.
Appendix F describes the TFTIF adapter boards that DSP Design have prepared for
a number of panel types.
The TV_CLK signal is an optional input to the CS5530A chip. It can be used as the
timing reference for the graphics sub-system, therefore enabling the Geode graphics
sub-system to be synchronised to external TV signals.
PIN SIGNAL PIN SIGNAL
1 ENABKL 2 ENAVDD
3 GND 4 SHFCLK
5 GND 6 LCD_HSYNC
7 GND 8 LCD_VSYNC
9 TV_CLK 10 FP_CLK_EVEN
11 RED0 12 RED1
13 GND 14 RED2
15 RED3 16 RED4
17 GND 18 RED5
19 GND 20 GND
21 GND 22 GREEN0
23 GREEN1 24 GREEN2
25 3.3V 26 GREEN3
27 GREEN4 28 GREEN5
29 3.3V 30 GND
31 GND 32 BLUE0
33 VCC 34 BLUE1
35 BLUE2 36 BLUE3
37 VCC 38 BLUE4
39 BLUE5 40 ENABLE
TABLE E11 - J8 FLAT PANEL CONNECTOR PIN ASSIGNMENTS