User guide
Table Of Contents
- Package Contents
- Other Supporting Documentation
- Evaluation Board Overview
- Functional Block Diagram
- Revision History
- Setting Up the Evaluation Board
- Standalone Mode
- I2C and SPI Control
- Automated Register Window Builder Software Installation
- Hardware Setup—USBi
- Powering the Board
- Resetting the Evaluation Board
- Setting Up the Master Clock (MCLK)
- Selecting PLL
- Routing Digital Audio Connections
- Connecting Analog Audio Cables
- Modification for Differential Output
- Modification to Use the N Output
- Schematics and Artwork
- Bill of Material
Evaluation Board User Guide UG-564
Rev. 0 | Page 9 of 32
SCHEMATICS AND ARTWORK
Figure 20. Schematic, Page 1—EVAL-ADAU196xAZ Block Diagram
ADAU196xA
DAC DIFF OUTPUT 1 TO 8 PASSIVE RC 1 POLE
DAC DIFF OUTPUT 9 TO 16 PASSIVE RC 1 POLE
POWER SUPPLY REGULATORS
5V = SWITCHING SUPPLY
3.3V = LINEAR SUPPLY DERIVED FROM 5V
INT REG
XISTOR
PLLVDD
DVDD
AVDD = 3.3V
IOVDD = 3.3V
0Ω JUMPERS FOR EACH SUPPLY
FOR CURRENT MEASUREMENT
USBi CONTROL PORT,
PD JUMPERS,
SA_MODE JUMPERS,
COM PORT JUMPERS,
RESET SWITCH
S/PDIF RECEIVER
DSP/FPGA INTERFACE
BCLK, LRCLK,
SDATA JUMPERS
WITH BUFFER
12V DC
INPUT
OPTICAL AND COAX INPUTS,
HARDWARE MODE
CONTROL JUMPERS
ALLOWS FOR
DIRECT
CONNECT TO DUT
SINGLE-ENDED OUTPUTS ON TRS MINI JACKS
3.3V FOR S/PDIF CORE
IOVDD COMES FROM DUT IOVDD
DESKTOP SUPPLY
24V DC INPUT MAX!
CM OUTPUT ON TP
BUFFERED MCLKO
CLKs
CLKs AND DATA
3.3V/2.5V
SINGLE-ENDED OUTPUTS ON TRS MINI JACKS
MCLK SOURCES
S/PDIF
ACTIVE OSC
CRYSTAL
DSP INTF
EXT IN
11588-020