User guide

UG-564 Evaluation Board User Guide
Rev. 0 | Page 6 of 32
SETTING UP THE MASTER CLOCK (MCLK)
The MCLK routing on the evaluation board is handled by a
block of jumpers, J5, allowing any one of four sources to be
selected—S/PDIF, the SMA connector, active OSC, and the
INTF connector. The board arrives with S/PDIF selected as
shown in Figure 10.
Figure 10. SPDIF Selected as MCLK Source
The evaluation board has a 12.288 MHz active oscillator that
can be selected by shorting the OSC_EN jumper JP8 and
selecting OSC on J5 as shown in Figure 11.
Figure 11. Active OSC Enabled and Selected as MCLK
The evaluation board can be set to receive MCLK from the SDP
interface connectors. To do so, select the INTF setting on J5 and
enable the MCLK buffer by shorting jumper J6, MCLK_SEL, as
shown in Figure 12.
Figure 12. INTF Input Enabled and Selected
SELECTING PLL
The PLL in the ADAU196xA is very flexible, allowing the
part to run from a wide range of either MCLK or LRCLK
frequencies.
It is also possible to shut the PLL off altogether and use the part
in direct lock mode; functionality with no PLL is limited to
256 × f
S
.
Figure 13. MCLK Selection for PLL Loop Filter
By default, the ADAU196xA runs from the PLL using MCLK as
the clock source. The MCLK loop filter must be selected using
JP2 as shown in Figure 13.
Figure 14. LRCLK Selection for PLL Loop Filter
DLRCLK can be selected as the PLL clock source using the PLL
and Clock Control 0 Register [7:6]. In this case, the LRCLK
loop filter must be selected as shown in Figure 14. If DLRCLK is
selected as the PLL clock, there is no need for an MCLK.
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