User guide

Evaluation Board User Guide UG-564
Rev. 0 | Page 5 of 32
POWERING THE BOARD
The E VA L-ADAU196xAZ evaluation board requires a power
supply input of +12 V dc and ground to the power jack; +12 V
draws ~150 mA at higher sample rates with all channels
running.
The on-board regulators provide 5 V and 3.3 V rails. The 5 V rail
is derived from +12 V by a switching regulator; it supplies 5 V
for the 3.3 V power supply and other peripherals via the SDP
interface optional resistors R133 and R156. The 3.3 V rail is
derived from the 5 V supply by an LDO linear regulator; it
provides voltage to AVDD and IOVDD as well as other active
peripherals.
AVDD and IOVDD are connected on the board using 0R00 Ω
0805 package resistors. Should a need arise to insert a different
power source, or measure current draw of the entire board, it
can be accomplished using these 0 Ω jumpers.
Figure 6. AVDD and IOVDD Jumper Resistors
The ADAU196xA has an internal voltage regulator that allows
the user to derive DVDD and PLLVDD from the AVDD voltage
source. The external PNP transistor Q1 and and the passives,
C36, C40, and R56, make the regulator circuit shown in
Figure 7. Both JP9 and JP11 must be shorted to activate the
circuit; JP9 supplies the emitter of the PNP and JP11 powers
VSUPPLY (Pin 25) on the ADAU196xA.
Figure 7. ADAU196xA Internal Regulator Jumpers
Links are provided along each ADAU196xA power rail to
provide access for current measurement of only the
ADAU196xA (see Figure 8). These links also allow the user to
directly supply voltage from an outside source. The square pins
and the test points are the load side. All four links must be
connected for proper operation.
Figure 8. ADAU196xA Power Links
RESETTING THE EVALUATION BOARD
The E VA L-ADAU196xAZ has provisions for resetting and
powering down the ADAU196xA. S2 on the evaluation board,
shown in Figure 9, is a momentary reset switch that pulls the
master reset (
MR
) line low; this line controls the reset generator
U10.
MR
is also connected to the USBi and the SDP interface
connectors through steering diodes and protection resistors so
that outside devices can control the reset state of the evaluation
board as shown in
Figure 25. The power-down jumper JP5
allows the
MR
line to be tied low. The output of the reset
generator drives the PU/
RST
line.
The PU/
RST
line is directly connected to two devices: the
S/PDIF receiver and the ADAU196xA. The line is held low by a
pull-down resistor until the reset generator U10 asserts the line
high as shown in Figure 25. The PU/
RST
line is also connected
to a pin on the SDP interface through a steering diode and
protection resistor allowing external reset control.
Figure 9. Reset Switch and Power-Down Jumper
REGULATOR
OUTPUT
REGULATOR SIDE
LOAD SIDE
1
1588-006
11588-007
1
1588-008
11588-009