User guide
Table Of Contents
- Package Contents
- Other Supporting Documentation
- Evaluation Board Overview
- Functional Block Diagram
- Revision History
- Setting Up the Evaluation Board
- Standalone Mode
- I2C and SPI Control
- Automated Register Window Builder Software Installation
- Hardware Setup—USBi
- Powering the Board
- Resetting the Evaluation Board
- Setting Up the Master Clock (MCLK)
- Selecting PLL
- Routing Digital Audio Connections
- Connecting Analog Audio Cables
- Modification for Differential Output
- Modification to Use the N Output
- Schematics and Artwork
- Bill of Material
UG-564 Evaluation Board User Guide
Rev. 0 | Page 18 of 32
Figure 29. Schematic, Page 10—Power Supply
3v3 Linear Supply
5v0 Switching Supply
+12VDC MAX
GND
Plane decoupling
C117
C116
C114
47uF
C108C105
+
C119
47uF
D1
TP88
TP2
L2
600 Ohm @ 100 MHz
L5
600 Ohm @ 100 MHz
C1
+
C107
47uF
+
C118
47uF
TP8
TP9
R13
475R
D5
Green Diffused
R18
475R
D6
Green Diffused
TP60
TP86
TP92 TP5
TP1
TP3
TP17
TP6
TP4
TP13 TP56
TP23
TP94 TP36
2
1
3
J13
R124
243R
+
C115
10uF
3
OUT
1
ADJ
2
IN
U9
LM317MDT
R123
402R
7
GND
8
IN
6
SD
4
FB
1
SWITCH
2
BOOST
3
BIAS
5
COMP
U8
ADP3050ARZ
C106
68nF
C104
390pF
R120
1k15
R121
10k2
R122
32k4
D8
BAT54T1G
C109
0.47uF
C113
47uF
1 2
L6
22uH
MSS12778-223MLB
D7
1N5819HW-7-F
R14
0R00
R15
0R00
C152 C154 C121 C143
TP15
TP14
TP106TP105
TP102
TP104
5V0DD
3V3DD
+12VDC
3V3DD
5V0DD
IOVDD
AVDD
11588-029