User guide
Table Of Contents
- Package Contents
- Other Supporting Documentation
- Evaluation Board Overview
- Functional Block Diagram
- Revision History
- Setting Up the Evaluation Board
- Standalone Mode
- I2C and SPI Control
- Automated Register Window Builder Software Installation
- Hardware Setup—USBi
- Powering the Board
- Resetting the Evaluation Board
- Setting Up the Master Clock (MCLK)
- Selecting PLL
- Routing Digital Audio Connections
- Connecting Analog Audio Cables
- Modification for Differential Output
- Modification to Use the N Output
- Schematics and Artwork
- Bill of Material
UG-564 Evaluation Board User Guide
Rev. 0 | Page 16 of 32
Figure 27. Schematic, Page 8—SDP Interface Connectors
EI3 1A
SPORT1_D0
SPORT1_D1
SPORT1_CLK
SPORT1_FS
SPORT0_D1
SPORT0_D0
SPORT0_FS
SPORT0_CLK
SPI0_SEL_A
SPI0_MISO
SPI0_MOSI
SPI0_CLK
SDA0'
SCL0'
RESET_OUT'
DAU_MCLK
SPI0_SEL_B
SPI0_SEL_C
R133
OPEN
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1606
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J6
HIROSE_FX8-120S-SV(21)_SOCKET
D9
Schottky
R131
49R9
EI3_IOVDD
5V0DD
[7]
EI3_SCL
[7]
EI3_SDA
[7]
EI3_DSDATA1
[7]
EI3_DSDATA2
[7]
EI3_DSDATA3
[7]
EI3_DSDATA4
[7]
EI3_CLATCH_A
[7]
EI3_CDATA
[7]
EI3_CCLK
[7]
EI3_COUT
[6]
MR
[7]
EI3_DLRCLK0
[7]
EI3_DBCLK0
[7]
EI3_DLRCLK1
[7]
EI3_DBCLK1
[7]
EI3_MCLK
[7]
EI3_CLATCH_B
[7]
EI3_CLATCH_C
EI3 1B
SPORT3_D0
SPORT3_D1
SPORT3_CLK
SPORT3_FS
SPORT2_D1
SPORT2_D0
SPORT2_FS
SPORT2_CLK
SDA0'
SCL0'
RESET_OUT'
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J8
HIROSE_FX8-120S-SV(21)_SOCKET
R156
OPEN
+
C132
47uF
5V0DD
EI3_IOVDD
[7]
EI3_DSDATA5
[7]
EI3_DSDATA6
[7]
EI3_DSDATA7
[7]
EI3_DSDATA8
[7]
EI3_DLRCLK2
[7]
EI3_DLRCLK3
[7]
EI3_DBCLK2
[7]
EI3_DBCLK3
11588-027