User guide
Table Of Contents
- Package Contents
- Other Supporting Documentation
- Evaluation Board Overview
- Functional Block Diagram
- Revision History
- Setting Up the Evaluation Board
- Standalone Mode
- I2C and SPI Control
- Automated Register Window Builder Software Installation
- Hardware Setup—USBi
- Powering the Board
- Resetting the Evaluation Board
- Setting Up the Master Clock (MCLK)
- Selecting PLL
- Routing Digital Audio Connections
- Connecting Analog Audio Cables
- Modification for Differential Output
- Modification to Use the N Output
- Schematics and Artwork
- Bill of Material
Evaluation Board User Guide UG-564
Rev. 0 | Page 15 of 32
Figure 26. Schematic, Page 7—Level Shift and Clock Direction Control
1
VCCA
2
DIR
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10
A8
11
GND
12
GND
13
GND
14
B8
15
B7
16
B6
17
B5
18
B4
19
B3
20
B2
21
B1
22
OE
23
VCCB
24
VCCB
U13
SN74LVCH8T245DBR_8BITLVLSHFT
R143
49R9
R142
49R9
R137
10k0
R134
10k0
2
SCLA
3
SDAA
7
SCLB
6
SDAB
1
VCCA
8
VCCB
4
GND
5
EN
U15
PCA9517DP-T_I2CBUSRPT_LVLTRANS_TSSOP8
R144
10k0
1
VCCA
2
DIR
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10
A8
11
GND
12
GND
13
GND
14
B8
15
B7
16
B6
17
B5
18
B4
19
B3
20
B2
21
B1
22
OE
23
VCCB
24
VCCB
U16
SN74LVCH8T245DBR_8BITLVLSHFT
R139
10k0
2
A1
3
A2
7
B1
6
B2
1
VCCA
8
VCCB
4
GND
5
DIR
U11
SN74LVC2T45DCTR_2BITLVLSHFT
R127
10k0
R146
1k50
R145
3k32
1
VCCA
2
DIR
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10
A8
11
GND
12
GND
13
GND
14
B8
15
B7
16
B6
17
B5
18
B4
19
B3
20
B2
21
B1
22
OE
23
VCCB
24
VCCB
U17
SN74LVCH8T245DBR_8BITLVLSHFT
R149
10k0
R140
10k0
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R136
33R0
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R135
33R0
C135
C137
C138
C145
C142
C140
C122
C120
C146
C139
2
A
1
OE
4
Y
U14
SN74LVC1G125DRLR
R130
10k0
JP6
C136
C123
2
A
4
Y
1
OE
U12
SN74LVC1G126DRLR
R147
49R9
R148
49R9
R152
49R9
R128
49R9
R150
49R9
R151
49R9
TP96
TP95
[2,6]
USBI_SCL
[2,6]
USBI_COUT
[2,6]
USBI_SDA
EI3_IOVDD IOVDD
[8]
EI3_DSDATA1
[8]
EI3_DSDATA2
[8]
EI3_DSDATA3
[8]
EI3_DSDATA4
[8]
EI3_DSDATA5
[8]
EI3_DSDATA6
[8]
EI3_DSDATA7
[8]
EI3_DSDATA8
EI3_IOVDD IOVDD
[8]
EI3_SCL
[8]
EI3_SDA
EI3_IOVDD
IOVDD
IOVDDEI3_IOVDD
[6]USBI_5V00
EI3_SPI_EN
[5]
INTF_DLRCLK
[5]
INTF_DBCLK
IOVDD
IOVDD
IOVDD
EI3_IOVDD
[8]
EI3_DLRCLK0
[8]
EI3_DBCLK0
[8]
EI3_DBCLK1
[8]
EI3_DBCLK2
[8]
EI3_DBCLK3
[8]
EI3_DLRCLK1
[8]
EI3_DLRCLK2
[8]
EI3_DLRCLK3
[5]
INTF_DSDATA8
[5]
INTF_DSDATA7
[5]
INTF_DSDATA6
[5]
INTF_DSDATA5
[5]
INTF_DSDATA4
[5]
INTF_DSDATA3
[5]
INTF_DSDATA2
[5]
INTF_DSDATA1
[7,8]
EI3_MCLK
[6]
EI3_MCLKI
[7,8]
EI3_MCLK
[7]
MCLK_SEL
[7]
MCLK_SEL
EI3_IOVDD
[7]
MCLK_SEL
EI3_IOVD D EI3_IOVDD
[8]
EI3_CCLK
[2,6]
USBI_CCLK
[8]
EI3_CDATA
[8]
EI3_CLATCH_A
[8]
EI3_CLATCH_B
[8]
EI3_CLATCH_C
[2,6]
USBI_CLATCH_A
[2,6]
USBI_CDATA
[6]
EI3_MCLKO
[8]
EI3_COUT
USBI_CLATCH_B
USBI_CLATCH_C
11588-026