User guide
Table Of Contents
- Package Contents
- Other Supporting Documentation
- Evaluation Board Overview
- Functional Block Diagram
- Revision History
- Setting Up the Evaluation Board
- Standalone Mode
- I2C and SPI Control
- Automated Register Window Builder Software Installation
- Hardware Setup—USBi
- Powering the Board
- Resetting the Evaluation Board
- Setting Up the Master Clock (MCLK)
- Selecting PLL
- Routing Digital Audio Connections
- Connecting Analog Audio Cables
- Modification for Differential Output
- Modification to Use the N Output
- Schematics and Artwork
- Bill of Material
UG-564 Evaluation Board User Guide
Rev. 0 | Page 14 of 32
Figure 25. Schematic, Page 6—MCLK Selection, USBi Interface, CLKOUT Feed, and Reset Generator
MCLK sources
CLKOUT Feed
USBi or Aardvark
USBi Interface
MR line comes from USBi Board Reset
Reset
MCLK Source
Power down
12
34
56
78
J5
TP38
1
OE
2
GND
3
OUTPUT
4
VDD
U5
OSC_CPPFXC7-12.288MHZ_7MMX5MM_SMD
R42
49R9
L7
C33
Y1
12.288MHz
R49
150R
C29
22pF
C34
22pF
R53
49R9
2
A
1
OE
4
Y
U4
SN74LVC1G125DRLR
J2
R24
49R9
C111
TP20
1
3
5
7
9
2
4
6
8
10
J12
HEADER_10WAY_POL
R111
3k01
R155
3k01
4
VCC
3
MR
1
GND
2
RESET
U10
ADM811R
C27
1
2
3 4
S2
R126
100k
R157
10k0
JP8
R46
10k0
R132
49R9
C124
10pF
R39
0R00
J4
R38
49R9
C28
10pF
R129
49R9
R43
0R00
JP5
R50
1M00
D10
MBR0530T1G
[2]
MCLKI/XTALI
IOVDD
[2]
XTALO
[2]
MCLKO
IOVDD
[9]
8416_MCLKI
[6,8]
MR
[2,7]
USBI_SCL
[2,7]
USBI_SDA
[2,7]
USBI_CCLK
[2,7]
USBI_CLATCH_A
[2,7]
USBI_CDATA
IOVDD
[2,9]
PU_RST
[6,8]
MR
IOVDD
[7]
EI3_MCLKI
[9]
OMCK_FEED
[2,7]
USBI_COUT
[7]
USBI_5V00
[7]
EI3_MCLKO
11588-025