Evaluation Board User Guide UG-564 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluating the ADAU1962A/ADAU1966A High Performance, Low Power Multibit Sigma-Delta DAC PACKAGE CONTENTS evaluation board must be connected to an external 12 V dc power supply and ground. On-board regulators derive 5 V and 3.3 V supplies for the ADAU196xA and peripherals.
UG-564 Evaluation Board User Guide TABLE OF CONTENTS Package Contents .............................................................................. 1 Powering the Board.......................................................................5 Other Supporting Documentation ................................................. 1 Resetting the Evaluation Board ...................................................5 Evaluation Board Overview ............................................................
Evaluation Board User Guide UG-564 SETTING UP THE EVALUATION BOARD STANDALONE MODE The ADAU196xA has a standalone mode, which allows the user to choose between a limited number of operation modes without the need for a control interface. Applying a jumper across JP21, as shown in Figure 2, pulls SA_MODE (Pin 46) high enabling standalone mode in the ADAU196xA. The SA_MODE selections are listed in Table 1. Table 1.
UG-564 Evaluation Board User Guide AUTOMATED REGISTER WINDOW BUILDER SOFTWARE INSTALLATION The Automated Register Window Builder is a program that launches a graphical interface for direct, live control of the ADAU196xA registers. The GUI content for a specific part is defined in a part-specific .xml file; these files are included in the software installation. To install the Automated Register Window Builder software, follow these steps: 1. 2. 11588-004 3. 4. Figure 4.
Evaluation Board User Guide UG-564 POWERING THE BOARD The EVAL-ADAU196xAZ evaluation board requires a power supply input of +12 V dc and ground to the power jack; +12 V draws ~150 mA at higher sample rates with all channels running. AVDD and IOVDD are connected on the board using 0R00 Ω 0805 package resistors. Should a need arise to insert a different power source, or measure current draw of the entire board, it can be accomplished using these 0 Ω jumpers.
UG-564 Evaluation Board User Guide SETTING UP THE MASTER CLOCK (MCLK) SELECTING PLL The MCLK routing on the evaluation board is handled by a block of jumpers, J5, allowing any one of four sources to be selected—S/PDIF, the SMA connector, active OSC, and the INTF connector. The board arrives with S/PDIF selected as shown in Figure 10. The PLL in the ADAU196xA is very flexible, allowing the part to run from a wide range of either MCLK or LRCLK frequencies.
Evaluation Board User Guide UG-564 ROUTING DIGITAL AUDIO CONNECTIONS The ADAU196xA evaluation board has two separate inputs for digital audio signals: the S/PDIF and the SDP interface. 11588-015 11588-017 The S/PDIF receiver can handle either of two options: S/PDIF uses the RCA jack, J1, and optical uses the Toslink jack, U1. The input is selected using S1 as shown in Figure 15. Figure 15. S/PDIF Input Selector Switch SW1 Figure 17.
UG-564 Evaluation Board User Guide CONNECTING ANALOG AUDIO CABLES R5 OPEN 10µF DACN C3 OUTP OPEN + R2 OPEN R6 0Ω OUTN R3 49.9kΩ R4 OPEN Figure 19. Typical Evaluation Board Filter MODIFICATION TO USE THE N OUTPUT To evaluate the differential outputs, one can modify the board to accomplish this with a little soldering and a few parts. MODIFICATION FOR DIFFERENTIAL OUTPUT The ADAU196xA evaluation board can be modified to be used differentially.
Evaluation Board User Guide UG-564 SCHEMATICS AND ARTWORK 12V DC INPUT POWER SUPPLY REGULATORS 5V = SWITCHING SUPPLY DESKTOP SUPPLY 24V DC INPUT MAX! MCLK SOURCES S/PDIF ACTIVE OSC CRYSTAL DSP INTF EXT IN 3.3V = LINEAR SUPPLY DERIVED FROM 5V 0Ω JUMPERS FOR EACH SUPPLY FOR CURRENT MEASUREMENT IOVDD = 3.3V BUFFERED MCLKO AVDD = 3.3V 3.
JP9 + C40 Q1 TP53 ADAU1966 Voltage Regulator 1k50 R56 E ZX5T953GTA [2] VSUPPLY B [6,7] USBI_CLATCH_A [6,7] USBI_CCLK [6,7] USBI_SCL [6,7] USBI_COUT USBI_SDA [6,7] [6,7] USBI_CDATA GND IOVDD 1 3 5 7 9 11 13 15 17 19 21 23 25 27 2 4 6 8 10 12 14 16 18 20 22 24 26 28 HEADER_28WAY_UNSHROUD J11 TDM4, Pulse TDM8, Pulse TDM16, Pulse TDM8, 50% Duty Cycle 0 I2S 1 TDM Pin 45 00 01 10 11 0 No Func tion, can be set to 0 or 1 1 No Funct ion Pin 44 Pins 32:3 1 0 256x fs, PLL 1 384x fs, PLL
Figure 22. Schematic, Page 3—ADAU196xA DAC Output 1 to Output 8 DAC4N [2] DAC4P [2] DAC3N [2] DAC3P [2] DAC2N [2] DAC2P [2] DAC1N [2] TP85 TP84 TP83 TP82 TP81 TP80 TP79 C87 OPEN R98 2.7nF 475 R R97 OPEN R96 2.7nF C86 475 R R95 OPEN R94 2.7nF C85 475 R R93 OPEN R92 2.
DAC12N [2] DAC12P [2] DAC11N [2] DAC11P [2] DAC10N [2] DAC10P [2] DAC9N [2] DAC9P [2] TP39 TP41 TP46 TP48 TP51 TP54 TP58 OPEN R40 C31 2.7nF 475R R44 OPEN R47 C38 2.7nF 475R R51 OPEN R54 C48 2.7nF 475R R57 OPEN R60 C54 2.
[7] 8416_SDATA INTF_DSDATA1 [9] B C7 JP22 IOVDD 2 A 1 Y OE U18 4 SN74LVC1G125DRLR [7] INTF_DSDATA2 [7] INTF_DSDATA3 [7] INTF_DSDATA4 [7] INTF_DSDATA5 [7] INTF_DSDATA6 [7] INTF_DSDATA7 [7] INTF_DSDATA8 [9] 8416_LRCLK [7]INTF_DLRCLK [9] 8416_BCLK R141 DSDATA8 DSDATA1 C141 2.2pF 33R2 DSDATA2 DSDATA3 DSDATA4 DSDATA5 DSDATA6 DLRCLK DSDATA7 DBCLK JP10 A B JP12 A B JP13 A B JP14 A B JP15 A B JP16 A B JP17 A B JP18 A B JP19 A B JP20 A B Rev. 0 | Page 13 of 32 A Figure 24.
IOVDD [2,7] J4 R46 10k0 USBI_SCL [2,7] USBI_SDA [2,7] USBI_COUT [2,7] USBI_CCLK [2,7] USBI_CLATCH_A C33 1 GND OE VDD Rev. 0 | Page 14 of 32 R129 49R9 OUTPUT R42 49R9 C28 10pF R38 49R9 C124 10pF R43 R132 49R9 OMCK_FEED [9] 8416_MCLKI [9] 0R00 Figure 25.
C137 C138 MCLK_SEL [7] EI3_MCLK [7,8] 2 A 1 R137 EI3_IOVDD R130 10k0 EI3_IOVDD [8] EI3_CCLK [8] EI3_CLATCH_C [8] EI3_CLATCH_B [8] EI3_CDATA [8] EI3_CLATCH_A 4 R139 10k0 Y U14 SN74LVC1G125DRLR OE EI3_DSDATA1 EI3_DSDATA2 EI3_DSDATA3 EI3_DSDATA4 EI3_DSDATA5 EI3_DSDATA6 EI3_DSDATA7 EI3_DSDATA8 24 VCCA VCCB 23 DIR VCCB 22 OE A1 21 B1 A2 20 B2 A3 19 U13 B3 A4 18 B4 A5 17 B5 A6 16 B6 A7 15 B7 A8 14 GND B8 13 GND GND MCLK_SEL [7] EI3_IOVDD R147 IOVDD 10k0 R134 EI3_IOVD D SN74LVCH8T245DBR
Rev. 0 | Page 16 of 32 [6] MR Figure 27.
Figure 28. Schematic, Page 9—S/PDIF Receiver Rev. 0 | Page 17 of 32 C112 J1 CTP-021A-S-YEL 1 R6 75R0 1.
Rev. 0 | Page 18 of 32 J13 1 3 2 Figure 29. Schematic, Page 10—Power Supply GND TP88 TP2 +12VDC MAX D1 C1 +12VDC L2 600 Ohm @ 100 MHz 5V0DD L5 C107 47uF + 600 Ohm @ 100 MHz 3V3DD C105 + C118 47uF C106 68nF R120 1k15 C116 IN C104 390pF 2 + 5 6 7 8 U8 FB BIAS BOOST SWITCH 4 3 2 1 C109 0.
UG-564 11588-030 Evaluation Board User Guide Figure 30. Top Assembly Rev.
Evaluation Board User Guide 11588-031 UG-564 Figure 31. Top Layer Copper Rev.
UG-564 11588-032 Evaluation Board User Guide Figure 32. L2 Ground Rev.
Evaluation Board User Guide 11588-033 UG-564 Figure 33. L3 Power Rev.
UG-564 11588-034 Evaluation Board User Guide Figure 34. Bottom Copper Rev.
Evaluation Board User Guide 11588-035 UG-564 Figure 35. Bottom Assembly Rev.
Evaluation Board User Guide UG-564 BILL OF MATERIAL Table 2. Qty 1 Reference U6 1 J12 1 U5 2 J6, J8 1 U1 1 U2 10 JP1, JP3 to JP9, JP11, JP21 1 U8 1 J11 1 U9 11 JP2, JP10, JP12 to JP20 Description Multibit SigmaDelta DAC 10-way shroud, polarized header 12.288 MHz, fixed SMD oscillator, 3.3 V to 5 V dc 120-pin socket, 0.6 mm 15 Mbps fiber optic receiving module with shutter 192 kHz dgtl rcvr, 28-TSSOP 2-pin header, unshrouded, jumper ,0.
UG-564 Qty 2 Reference R13, R18 7 RS1 to RS7 1 R126 14 1 R4, R9, R20, R46, R127, R130, R134, R137 to R140, R144, R149, R157 R121 5 R10 to R12, R21, R49 1 R120 2 R56, R146 1 R50 1 R124 1 R122 5 R59, R62 to R63, R66, R141 3 R6, R111, R155 2 R25, R145 1 R123 16 R31, R33, R35, R37, R44, R51, R57, R64, R70, R76, R82, R88, R91, R93, R95, R97 R125 1 16 R8, R22, R26, R29, R45, R52, R58, R65, R71, R77, R83, R89, R100, R102 R104, R106 Evaluation Board User Guide Description Chip resi
Evaluation Board User Guide Qty 15 1 Reference R24, R38, R42, R53, R128 to R129, R131 to R132, R142 to R143, R147 to R148, R150 to R152 R27 8 R67, R72 to R73, R78 to R79, R84 to R85, R90 18 2 R39, R43, R107, R117 to R119, R158 to R161, R170 to R177 R14 to R15 1 S1 48 3 R7, R19, R23, R28, R30, R32, R34, R36, R40 to R41, R47, to R48, R54 to R55, R60 to R61, R68 to R69, R74 to R75, R80 to R81, R86 to R87, R92, R94, R96, R98 to R99, R101, R103, R105, R108 to R110, R112 to R116, R162 to R169 R133, R1
UG-564 Qty 2 Reference C113 to C114 44 C1, C4, C7, C11 to C12, C27, C33, C36 to C37, C40 to C42, C44, C47, C53, C65, C67 to C68, C71, C75, C77, C105, C108, C110 to C112, C116 to C117, C120 to C123, C135 to C140, C142 to C143, C145 to C146, C152, C154 C43, C45, C72, C76, C109 5 2 C5 to C6 1 C20 1 C2 2 C28, C124 3 C50, C52, C141 2 C29, C34 2 C17, C104 8 C56 to C58, C60, C63 to C64, C66, C70 1 C18 1 C3 16 1 C23 to C-26, C31, C38, C48, C54, C61, C73, C79, C82, C84 to C87 C106 1 C21
Evaluation Board User Guide Qty 1 1 Reference Q1 J1 1 D4 2 R135 to R136 2 J2, J4 1 L6 1 U12 1 D8 2 D9 to D10 1 D7 8 J3, J9 to J10, J14 to J18 1 D1 1 S2 1 D2 1 U10 Description PNP transistor RCA jack, PCB TH mount, R/A yellow Red diffused, 6.0 millicandela, 635 nm 1206 Resistor network, isolated 8 res, 33R0 SMA receptacle, straight PCB mount SMT power inductor, 22 µH Sngl bus, buff gate, 3ST SOP-5 Schottky 30 V, 0.2 A, SOD123 diode Schottky 30 V, 0.
UG-564 Evaluation Board User Guide NOTES Rev.
Evaluation Board User Guide UG-564 NOTES Rev.
UG-564 Evaluation Board User Guide NOTES I2C refers to a communications protocol developed by Philips Semiconductors (now NXP Semiconductors). ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD.
