Datasheet

Application Note 8 2015-02-11
Revision 1.0
ISO2H823V2.5 Evaluation Board
Board Manual
Functional Description
Figure 5 Timing by Parallel Write Access (e.g. DRIVE Register)
For a writing access to internal registers the MSB of the address register has to be set to “1”.
wr_timing_ifx - uc_parallel
/CS
AD[7:0]
ALE
/WR
t
AD_hd
t
WRhigh
t
WR_su
t
WR_hd
t
lat
DRIVE
DRIVE address (80 h)
t
AD_su
DRIVE data (0Fh)
t
AD_hd
t
AD_su
DRIVE data (0Ah)
00h
0Fh
t
CSD
OUT[7:0]
0Fh00h
t
WRlow
t
CS_ALE
t
ALE_high