Datasheet

Application Note 10 2015-02-11
Revision 1.0
ISO2H823V2.5 Evaluation Board
Board Manual
Functional Description
2.2.2 Serial Interface Mode
The ISO2H823V2.5 device contains a serial interface that can be activated by pulling the SEL pin to logic high
state. The interface can be directly controlled by the µController output ports. The output pin SDO is in state “Z”
as long as CS
=1. Otherwise, the bits at the SDI input are sampled with the rising edge of SCLK and registered
into the input FIFO buffer of length dependent on the selected SPI-mode (8, 16, 24 bits,
Figure 8, Figure 9,
Figure 10, Figure 11). With every falling edge of SCLK the bits to be read are provided serially to the pin SDO.
The timing requirements for the serial interface are shown in
Figure 7 and inside the chapter electrical
characteristics in the
ISO2H823V2.5 datasheet.
Figure 7 Serial Bus Timing
2.2.2.1 SPI Modes
Four different SPI-modes can be distinguished (Figure 8 - Figure 11).
Figure 8 SPI Mode 0, MS0 = 0, MS1 = 0, Daisy Chain Supported
tim ing_ def - uc _spi
transmit
edge
receive
edge
t
SCLK_valid
MSB
t
SU
t
HD
CS
SCLK
SDI
SDO
LSB
MSB LSB
t
CSD
t
float
t
CS_valid
inactive
active
t
SCLK
t
SCLK_su
t
CSH
SCLK
SDI
CS
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
MS B LS B
Channel-Value (Drive Information )
CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
MS B LS B
SDO
Collective Diagnosis
uc_spi_mode0.vsd