Schematics

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.Place 6.8ohm series termination resistors close to GRX350 for CA group.
2.An external RZQ 240 ohm+/-1% resistor shoudl be connect from the ZQ pin to ground on both GRX350 and DDR device.
3.System DD_VREF and DDR device VREFCA and VREFDQ are separated,divided by 10K ohm +/-1% resistors.
4.55 ohm Single-End and 100 ohm Differential signals impedance control
5.5mils Single-End trace width, trace to trace clearance is 10mils
6.Length Matching
Maximum trace length difference (skew) between DQS and DQS#: ± 4 mils (< 0.6 ps).
Maximum trace length difference (skew) DQ to DQS/ DQS# domain: ± 30 mils (< 10 ps).
Maximum trace length difference (skew) Addr/Cmd to CK/ CK# domain: ± 70 mils (< 25ps).
Maximum trace length difference (skew) DQS/DQS# to CK/ CK# domain: ± 250 mils (< 90ps).
7.Crosstalk control (Note: H is distance from reference layer):
Keep edge-to-edge trace spacing within DQ/DM byte group > 2H
Keep edge-to-edge trace spacing within Cmd/Add/Ctrl > 2H (commonly known as CA)
Keed edge-to-edge trace separation for each group (DQ, DQS/DQS#, CA, CK/CK#) > 3H
8.DDR CLK differential termination 100ohm place at the end on DDR device. as close to CLK pins as possible.
9.Fly-By Topology & VTT Termination recommended for DDR3, if multiple devices are used.
10.Carefully consider layout requirements of DDRn vendor!!!
Qualified DDR3 List
Etron: EM6GC16EWXD-10H (64Mx16bit, single rank (CS0))
Micron: MT41K128M16JT-125:K (128Mx16bit, single rank (CS0))
Micron: MT41K256M16HA-125 IT:E ( 256Mx16bit, single rank (CS0))
Winbond: W634GG6LB-12 (256Mx16bit, single rank (CS0))
Etron: EM6GE16EWXC-10H (256Mx16bit, single rank (CS0))
Nanya: NT5CB256M16DP-EK (256Mx16bit, single rank (CS0))
Micron: MT41K512M16HA-125:A (512Mx16bit, single rank (CS0))
Place R224 close to pin J7 and K7.
GND
GND
GND
GND
GND
GND
GND
DDR_1V5
DDR_1V5
DDR_1V5
DDR_1V5
GND
DDR_1V5
GND
GND
Title
Size Document Number Rev
Date: Sheet of
GRX350_DDR3_x16
6B
V2766AX
<OrgName>
Custom
3 34Thursday, July 21, 2022
Title
Size Document Number Rev
Date: Sheet of
GRX350_DDR3_x16
6B
V2766AX
<OrgName>
Custom
3 34Thursday, July 21, 2022
Title
Size Document Number Rev
Date: Sheet of
GRX350_DDR3_x16
6B
V2766AX
<OrgName>
Custom
3 34Thursday, July 21, 2022
R250
10k,1%
RN2
6.8R
1
2
3
4
8
7
6
5
R81
10k,1%
RN6 6.8R
1
2
3
4
8
7
6
5
C177
10nF
C210
10nF
C42
10uF
R260
240
C34
100nF
C184
100nF
C179
10nF
C207
100nF
TP12
Reference
VDDQ
VDD
VSSQ
VSS
Not Connected
U4B
DDR3,W632GG6NB-12
VDDQ
D2
VDD
D9
VSSQ
G1
VSSQ
G9
VDDQ
F1
VDDQ
H9
VSSQ
E2
VREFDQ
H1
VDD
K8
VDD
N9
VDD
K2
NC
L1
VDDQ
H2
VSS
T1
VSS
M9
VDD
N1
VDD
R1
NC
J1
VSS
J2
VSS
M1
VDD
R9
VSS
P9
VDDQ
A1
VDDQ
A8
VSS
A9
VSSQ
D1
VSS
E1
VSSQ
B1
VDD
B2
VSS
B3
VSSQ
B9
VSS
T9
VSS
P1
VSS
J8
NC
J9
NC
L9
VSS
G8
VSSQ
F9
VSSQ
D8
VDDQ
E9
VREFCA
M8
VSSQ
E8
VDD
G7
VDDQ
C1
VDDQ
C9
R105
6.8R
C37
100nF
C178
100nF
C36
470pF
R249
10k,1%
RN5 6.8R
1
2
3
4
8
7
6
5
C27
100nF
R95
0R
C175
100nF
C185
470pF
RN1 6.8R
1
2
3
4
8
7
6
5
C209
10nF
TP43
C240
100nF
C234
10nF
C168
10nF
R82
10k,1%
TP13
R248
10k
8-Gbit DDR3 SDRAM
512M x 16
U4A
DDR3,W632GG6NB-12
DQL2
F2
DQSL
G3
DQL4
H3
DQL6
G2
A0
N3
ODT
K1
CKE
K9
A7
R2
BA2
M3
BA0
M2
A5
P2
CS
L2
A6
R8
WE
L3
RESET
T2
DQU5
A2
DQU7
A3
DQU4
A7
DQSU
B7
DQU6
B8
A14
T7
A13
T3
A4
P8
A9
R3
CK
J7
DQL3
F8
A2
P3
A12/BC
N7
BA1
N8
A1
P7
DQL7
H7
RAS
J3
A10/AP
L7
CAS
K3
ZQ
L8
DQL1
F7
DQSL
F3
DMU
D3
DQU0
D7
A8
T8
A3
N2
CK
K7
DQL5
H8
A11
R7
DQU3
C2
DQU1
C3
DQSU
C7
DQU2
C8
DQL0
E3
DML
E7
A15
M7
C190
10nF
R94
0R
R252
100R
U5B
GRX350
DDA6
B3
DD_RAS
L1
DDA7
G1
DDA12
D2
DDQ13
U3
DDQ1
AB1
DD_DQS1_N
P2
DDQ3
AA3
DDQ10
P3
DDQ5
AB2
DD_DQS1_P
P1
DDQ7
AC2
DDQ4
Y3
DDQ9
T1
DDQ6
Y2
DDQ12
R2
DDQ2
W1
DD_DM1
T3
DD_DQS0_N
Y1
DDQ11
T2
DDA13
G2
DDA14
E3
DDA9
J3
DD_BA0
L3
DDA11
D3
DDA0
K2
DD_BA1
C4
DD_BA2
K1
DDA1
A5
DDA2
K3
DDA8
B2
DDA15
A2
DDA3
B1
DD_WE
C2
DD_CS
N3
DDQ8
N2
DDA5
H3
DDQ14
R3
DDQ0
W3
DD_DQS0_P
W2
DD_DM0
AA2
DDQ15
U2
DD_ODT0
L2
DD_CK_P
J2
DD_CK_N
H2
DDA4
A4
DD_ZQ
D1
DD_ODT1
B4
DD_CS1
E2
DDA10
C3
DD_CAS
D4
DD_RST
G3
DD_Vref
Y4
DD_CKE
E1
DD_CKE1
M8
DD_ATO
N8
C205
100nF
C180
10nF
C187
10nF
C241
100nF
R246
10k
C208
10nF
C242
100nF
C226
100nF
C191
10nF
C206
470pF
C186
10nF
RN3 6.8R
1
2
3
4
8
7
6
5
RN4 6.8R
1
2
3
4
8
7
6
5
R98
6.8R
TP42
R92
240
NETC3_1
NETR126_2
DDR_ZQ
DDR_RESET
NETR311_2
NETR324_2
NETR127_2
DDR_CLK_P_O
DDR_CLK_P_O
DDR_ADDR15
DDR_ADDR15
DDR_LDQS_N
DDR_UDQS_P
DDR_CLK_N_O
DDR_DQ0
DDR_DQ1
DDR_DQ2
DDR_DQ3
DDR_DQ4
DDR_DQ5
DDR_DQ6
DDR_DQ7
DDR_DQ8
DDR_DQ9
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQ0
DDR_DQ1
DDR_DQ2
DDR_DQ3
DDR_DQ4
DDR_DQ5
DDR_DQ6
DDR_DQ7
DDR_DQ8
DDR_DQ9
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_UDM
DDR_UDQS_P
DDR_UDQS_N
DDR_LDM
DDR_LDQS_P
DDR_LDQS_N
DDR_ADDR0
DDR_ADDR1
DDR_ADDR2
DDR_ADDR3
DDR_ADDR4
DDR_ADDR5
DDR_ADDR6
DDR_ADDR7
DDR_ADDR8
DDR_ADDR9
DDR_ADDR10
DDR_ADDR11
DDR_ADDR12
DDR_ADDR14
DDR_BA0
DDR_BA1
DDR_CAS
DDR_CLK_N_O
DDR_CKE
DDR_LDQS_P
DDR_UDM
DDR_UDQS_N
DDR_LDM
DDR_RAS
DDR_CS
DDR_BA2
DDR_WE_N
DDR_ADDR13
DDR_ODT
DDR_RESET
NETC191_1
DDR_ADDR1
NETRN5_2
NETRN5_1
NETRN5_3
NETRN4_2
NETRN4_3
NETRN4_4
NETRN6_1
NETRN6_2
NETRN6_3
NETRN6_4
NETRN6_4
NETRN4_1
NETRN7_2
NETRN7_3
NETRN7_4
NETRN7_1
NETRN8_1
NETRN8_2
NETRN8_3
NETRN8_4
NETRN9_1
NETRN9_2
NETRN9_2
DDR_CAS
DDR_ADDR6
DDR_BA1
DDR_ADDR4
NETRN9_1
NETRN9_3
NETRN9_4
NETRN9_4
NETRN9_3
DDR_ADDR0
DDR_BA2
DDR_ADDR2 NETRN5_3
NETRN5_2
NETRN5_1
DDR_ADDR9
DDR_ADDR7
DDR_ADDR13
DDR_ADDR5
NETRN6_3
NETRN6_2
NETRN6_1
DDR_CS
DDR_ODT
DDR_RAS
DDR_BA0
NETRN4_1
NETRN4_2
NETRN4_3
NETRN4_4
DDR_CKE
DDR_ADDR14
DDR_ADDR12
DDR_ADDR11
NETRN7_1
NETRN7_2
NETRN7_3
NETRN7_4
DDR_WE_N
DDR_ADDR10
DDR_ADDR3
DDR_ADDR8
NETRN8_1
NETRN8_2
NETRN8_3
NETRN8_4
NETTP3_1
NETTP74_1
NETTP5_1
DDR_ZQ1
NETC1_1