Schematics

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D D

C C

B B

A A

1.Add 24.9 ohm serial resistor on RGMII

TX signals (TXCLK, TXCTL, TXD0TXD3)

near GRX350

2.50 ohm impedance for RGMII signal

routing. Keep the reference plane of

RGMII signal continuous.

3.The RGMII RX/TX signals should be

routed along with a solid reference GND

plane to have precise impedance

matching. It will be good to route all the

trace in one single layer. If layer

interchanged is necessary for trace

routing, minimizing via count is absolutely

needed. Populate sufficient GND vias to

tighten different GND planes nearby the

location of layer interchanged.

1.Defines FL_CS1 (GPIO23) as only CS

for a Parallel NAND Flash.

2.FL_RDBY and FL_WP pull high by 10K

ohm resistor.

3.Add bypass capacitors for the power

supply pins of NAND Flash and place

them closer to power supply pins.

4.Leave all NAND Flash signals away

from high-speed digital signals, analog

signals, and power traces.

An external Rcal 16K ohm+/-1%

resistor shoudl be connect from

the RCAL pin to ground.Place

the Rcal resistor clase to RCAL

ball.

1.100 ohm characteristic

impedance control for TPI

differential signal routing. Keep

the reference plane of signal

continuous.

2.The TPI signals should be

routed along with a solid

reference GND plane to have

precise impedance matching. It

will be good to route all the

trace in one single layer. If layer

interchanged is necessary for

trace routing, minimizing via

count is absolutely needed.

Populate sufficient GND vias to

tighten different GND planes

nearby the location of layer

interchanged.

HEATSINK CLIPS

for 654 EVB FW

"1" for VRX518 detect

"0" for VRX618 detect

+3V3_FLASH

GND

+3V3

GND

NFLASH_IO[7..0] [8]

NFLASH_RDBY_N [8]

NFLASH_WE_N [8]

NFLASH_WP_N [8]

NFLASH_CS1_N [8]

NFLASH_RE_N [8]

NFLASH_ALE_N [8]

NFLASH_CLE_N [8]

GTP3_AP[11]

GTP3_DN[11]

GTP3_DP[11]

GTP3_BP[11]

GTP3_BN[11]

GTP3_AN[11]

GTP2_AN[11]

GTP2_CP[11]

GTP2_CN[11]

GTP2_DP[11]

GTP2_DN[11]

GTP2_BN[11]

GTP2_BP[11]

GTP2_AP[11]

GTP1_AN[11]

GTP1_CP[11]

GTP1_CN[11]

GTP1_DN[11]

GTP1_DP[11]

GTP1_BN[11]

GTP1_BP[11]

GTP1_AP[11]

GTP3_CN[11]

GTP3_CP[11]

GTP0_AP[11]

GTP0_CN[11]

GTP0_CP[11]

GTP0_DP[11]

GTP0_DN[11]

GTP0_BN[11]

GTP0_BP[11]

GTP0_AN[11]

PCIE2_RST_N_AXE [12]

GTP4_AP11

GTP4_CP11

GTP4_CN11

GTP4_DN11

GTP4_DP11

GTP4_BP11

GTP4_BN11

GTP4_AN11

Title

Size Document Number Rev

Date: Sheet of

GRX350_NAND_xMII_GPH

V2766AX

Custom

2 34Thursday, July 21, 2022

Title

Size Document Number Rev

Date: Sheet of

GRX350_NAND_xMII_GPH

V2766AX

Custom

2 34Thursday, July 21, 2022

Title

Size Document Number Rev

Date: Sheet of

GRX350_NAND_xMII_GPH

V2766AX

Custom

2 34Thursday, July 21, 2022

R267

4.7k,5%

R272

4.7k,5%

R251

16K,1%

R661

(6)0R

R662

(5)4.7K

GPHY NAND

xMII0

xMII6F

U5A

GRX350

GPIO61/FL_SE/LED_BD

GPIO53/FL_D7

GPIO54/FL_D6

GPIO49/FL_RE

GPIO56/FL_D4

GPIO13/FL_ALE

GM6FT7

M20

xM6FTE

R19

wMDIO

W18

xM6FTC

T19

xM6FT2

T20

xM6FT3

V20

xM6FR2

AC20

xM6FR3

AB21

TPIAP6F

AC22

xM6FRC

AB19

TPIBN3

L22

TPIAN3

M22

TPICP4

P22

TPIDN4

N23

TPIDP4

N22

TPICP3

L23

TPICN3

K21

TPIDN3

K22

TPIBN2

H21

TPICP2

G23

TPIAP2

J22

TPICN2

G22

TPIDP2

F22

TPIDN5

T22

TPICN4

P23

TPIAN4

R21

TPIBP4

R22

TPIBN5

V22

TPIDP5

U23

TPIAP5

W21

TPICN5

U22

TPIDN6F

Y23

TPIBP5

W22

TPICN6F

Y21

TPIDP6F

Y22

TPIBN6F

AA21

TPICP6F

AA22

TPIBP6F

AB23

TPIAN6F

AB22

GM6FRER

W20

TPIDP3

K23

TPIDN2

F21

TPIBP3

L21

TPIBP2

H23

TPIAN2

H22

TPIAP3

M21

TPIBN4

P21

TPIAP4

T23

TPICP5

U21

TPIAN5

W23

F20

E21

D21

J19

K20

GM6FT5

P20

xM6FT0

U19

wMDC

Y17

F19

L20

H19

GM6FT6

N20

GM6FT4

R20

GM6FR4

AA20

GM6FR5

W19

xM6FT1

U20

GM6FR7

Y20

xM6FRV

AB20

xM6FR1

AA19

GM6FR6

V19

xM6FR0

AC19

GPIO51/FL_D0

GPIO50/FL_D1

GPIO52/FL_D2

GPIO57/FL_D3

GPIO55/FL_D5

GPIO24/FL_CLE

GPIO48/FL_RDBY

GPIO59/FL_WE

GPIO60/FL_WP

GPIO23/FL_CS1

H20

G19

J20

G20

RCAL

P19

NFLASH_IO5

NFLASH_IO[7..0]

NFLASH_RDBY_N

GTP1_DN

GTP1_DP

GTP1_CP

GTP1_CN

GTP1_BN

GTP1_BP

GTP1_AN

GTP1_AP

GTP2_BN

GTP2_BP

GTP2_AN

GTP2_AP

GTP2_DP

GTP2_DN

GTP2_CP

GTP2_CN

GTP3_BP

GTP3_BN

GTP3_AP

GTP3_AN

GTP3_DN

GTP3_DP

GTP3_CN

GTP3_CP

NFLASH_IO0

NFLASH_IO1

NFLASH_IO2

NFLASH_IO3

NFLASH_IO4

NFLASH_IO6

NFLASH_IO7

NFLASH_WE_N

NFLASH_RE_N

NFLASH_ALE_N

NFLASH_CLE_N

NFLASH_CS1_N

NFLASH_WP_N

NETR119_2

GTP0_DP

GTP0_DN

GTP0_CN

GTP0_CP

GTP0_BN

GTP0_BP

GTP0_AP

GTP0_AN

GTP4_AP

GTP4_BP

GTP4_BN

GTP4_AN

GTP4_DN

GTP4_DP

GTP4_CP

GTP4_CN

GPIO_31

Summary of content (30 pages)

PAGE 1
5 4 3 2 1 U5A NFLASH_IO[7..0] NFLASH_IO[7..0] GPHY 11 11 11 11 11 11 11 11 D 1.100 ohm characteristic impedance control for TPI differential signal routing. Keep the reference plane of signal continuous. 2.The TPI signals should be routed along with a solid reference GND plane to have precise impedance matching. It will be good to route all the trace in one single layer. If layer interchanged is necessary for trace routing, minimizing via count is absolutely needed.
PAGE 2
5 4 3 2 1 U5B DDR_ADDR1 NETRN5_3 NETRN5_2 NETRN5_1 NETR126_2 NETRN5_3 NETRN8_3 NETRN9_4 NETRN6_4 NETRN6_4 NETRN6_3 NETRN6_2 NETRN6_1 NETRN9_4 NETRN9_2 NETRN6_2 NETRN8_4 NETRN6_1 NETRN8_2 NETRN9_3 NETRN9_2 NETRN9_1 NETRN7_4 NETRN7_3 NETRN6_3 NETRN7_2 NETR127_2 K2 A5 K3 B1 A4 H3 B3 G1 B2 J3 C3 D3 D2 G2 E3 A2 NETRN4_4 NETRN9_3 NETRN5_1 L3 C4 K1 NETR324_2 NETR311_2 H2 J2 NETRN5_2 D DDR_ADDR2 DDR_ADDR0 DDR_BA2 DDR_ADDR5 DDR_ADDR13 DDR_ADDR7 DDR_ADDR9 DDR_ADDR4 DDR_BA1 DDR_ADDR6 DDR_CAS 6.
PAGE 3
5 4 3 VDD115 C182 C235 C228 C229 C219 C194 C195 C196 C197 C199 C198 C200 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF GND VDD115 D C248 10uF C216 C224 C223 C232 C238 C237 C250 100nF 100nF100nF100nF100nF100nF100nF C249 C257 C256 C255 100nF 100nF 100nF 100nF GND VDDL_1V15 C220 10nF C221 C222C231 C230 C236 100nF 10nF 10nF100nF 100nF VDDL_1V15 GND VDDH_3V3 VDD33 C253 C243 C261 C218 C193 C192 10nF10nF 10nF 100nF 100nF 100nF VDDH_3V3 C171 C202 10nF 10nF C246 100nF C245 100nF VDD3
PAGE 4
5 4 3 2 1 D D U5D B23 B22 A22 B21 [9] [9] USB_DP0 USB_DM0 USB_DP0 USB_DM0 OC_SENSE1 [9] D22 C22 R101 200R,1% GND OC_SENSE1 NETR10_1 D23 AC7 A20 A19 C19 B19 USB_DP1 [9] [9] USB_DP1 USB_DM1 C C20 B20 USB_DM1 OC_SENSE2 [9] R102 GND 200R,1% OC_SENSE2 C21 AC8 PCIe1 P_cP1 P_cN1 P_tP1 P_tN1 P_rP1 P_rN1 USB0 USBtP0 USBtN0 USBrP0 USBrN0 DP0 DM0 RREF1 RREF0 OC_SC0 PCIe2 P_cP2 P_cN2 P_tP2 P_tN2 P_rP2 P_rN2 USB1 USBtP1 USBtN1 RREF2 USBrP1 USNrN1 PCIe3 P_cP3 P_cN3 P_tP3 P_tN3 P_rP3 P_
PAGE 5
4 3 2 1 D D U5E AA17 AB17 AC16 AC17 AB18 AB15 C AA15 AC14 AB14 AB16 AC13 AB13 AB12 AA13 AA14 Trace capacitance for BBIO interface must be below 10pF! Recommend the maximum length should be under 3 inch.
PAGE 6
5 4 3 2 1 U5F for 654 EVB FW [16] RST_TO_DEFAULT_1 SLIC_RESET RST_TO_DEFAULT_AXE AB3 AA5 Y11 Y18 AB8 AA8 Y9 Y10 AB5 AB4 AB6 AA7 USB1_CTRL GPIO3 GPIO4 TP8 [12] D SLIC_CLK GPIO5 GPIO6 USB2_CTRL 0/0402 [8] SPI_Flash_CS1 [8,10] SPI_DIN [8,10] SPI_DOUT [8,10] SPI_CLK +3V3 RESET_IN R53 GPIO18 GPIO19 R52 C17 +3V3 [8,10] GPIO16_RST [8,10] GPIO17_RST [8,10] GPIO18_RST NULL/470pF [12] GND 47k,1% GPIO16 GPIO17 DGSP_RST C16 NULL/10uF GND C19 SLIC_TX NULL/33pF GND N.M.
PAGE 7
5 4 3 2 1 NFLASH_IO[7..0] D [2] NFLASH_IO[7..
PAGE 8
4 3 2 1 !!Note: The PCB layout of the differential signal DP and DM should have 90 ohm differential impedance, and keep the trace length below 1 inch if possible. USB_VOUT_B Bottom USB2.0 4 TOP B Bottom A USB Device Connector 4 Port A + R151 J7A VCC DATADATA+ GND 0R 1 2 3 4 CH1 USB_DM1 NULL_CM-CHOKE USB_DP1 10 0.1uF GND GND Dual_USB_Connector GND C105 9 EC10 V560uF/6.3V R150 0R C95 USB_DM1 6 USB_DP1 6 C90 Null/5pF Null/5pF USB_VOUT_A TOP USB2.0 3 C100 Port B 0.
PAGE 9
5 4 3 2 1 LED1 +3V3 ACT SOUT23 2 NULL/150ohm R24 C31 100nF 16 GND D [7] LED_D [7] LED_SH [7] LED_ST [7] POR_OUT_4 LED_D LED_SH LED_ST POR_OUT_4 14 11 12 10 13 8 LED_D <--> GPIO5 LED_ST <--> GPIO4 LED_SH <--> GPIO6 R83 NULL/0R 1 GND GreenNULL/SLED_0603_G GND U17 VCC 15 1 2 3 4 5 6 7 9 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7 DS SHCLK STRCLK MR OE SOUT23 SOUT22 SOUT21 SOUT20 LED2 SOUT15 SOUT18 WAN SOUT16 GND SOUT20 R23 1 YELLOW NULL/150ohm 1 2 R28 3 GREEN NULL/120ohm 3 4 GND 4 D
PAGE 10
8 7 6 5 4 3 2 1 C70 1000pF/2KV GND GND 3 3 4 GTP0_CN GTP0_CP 3 3 GTP0_BN GTP0_BP 3 3 GTP0_AN GTP0_AP 3 3 GTP1_CN GTP1_CP 3 3 GTP1_BN GTP1_BP 3 3 GTP1_AN GTP1_AP GTP0_BN GTP0_BP GND C65 68pF GND C286 68pF 3 3 GTP2_CN GTP2_CP 3 3 GTP2_BN GTP2_BP 3 3 R107 R100 GTP2_AN GTP2_AP 68pF NULL/16K NULL/16K GND C60 68pF GTP1_CN GTP1_CP GND C285 68pF GTP1_BN GTP1_BP GND C47 68pF GTP1_AN GTP1_AP GND C274 68pF R85 R80 1 2 3 4 5 6 7 8 9 10 11 12 68pF GND GTP1_DN GTP1_
PAGE 11
4 3 2 PoE-PD (PD)SCD310/3A/100V PD2 (PD)SCD310/3A/100VPD10 PC15 (PD)1000PF 2KV (PD)SCD310/3A/100V CO-LAY GND PD4 48V_V- GND PC2 (PD)680pF/50V/0805 PEC2 POE_GND POE_GND 2 2 12 PD7 PR8 (PD)BAV20WS/200V/2.5A(PD)10/1%/0603 1 2 1 PD6 (PD)SCD310/3A/100V PC1 (PD)10uF/25V/1206 + PEC1 (PD)220uF/16V/0625/LL GND 10 (PD)UT35L35 GND PC3 PC12 (PD)0.1uF/25V/0402 (PD)10uF/25V/1206 TP5 2 6 5 POE_GND VC 1 PD8 (PD)4.
PAGE 12
5 4 3 2 WAVE654 PCIE / GPIO / SPI WAVE654 POWER XC167 XU14A FSYS_OUT_P E36 XTP13 FSYS_IN_N E37 FSYS_IN_P D51 XTP12 XTP11 GPIO13 GPIO14 GPIO15 FSYS_OUT2_N FSYS_OUT2_P FSYS_IN_N XTAL1 FSYS_IN_P XTAL2 VDDRF1V5HBANT3 VDD0V9_9 VDDRF1V5LBANT0 VDD0V9_10 VDDRF1V5LBANT1 VDD0V9_11 VDDRF1V5LBANT2 VDD0V9_12 VDDRF1V5LBANT3 VDD0V9_13 VDDRF1V5RXANT0 VDD0V9_14 VDDRF1V5RXANT1 VDD0V9_15 VDDRF1V5RXANT2 VDD0V9_16 VDDRF1V5RXANT3 BB3V3PLL (AX)0R/0402/5% GND GND XC110 XC180 XC135 XC112 GN
PAGE 13
4 [18] FECTL_0_4 2G_LNA0 [18] FECTL_0_5 [20] FECTL_1_0 5G_PE1 [20] FECTL_1_1 5G_LNA1 [20] FECTL_1_2 FECTL_0_3 C6 FECTL_0_4 C7 FECTL_0_5 D7 FECTL_1_0 C9 FECTL_1_1 D10 FECTL_1_2 C10 A11 C12 D12 E4 D17 E5 2G_CR2 [19] FECTL_2_3 2G_PE2 [19] FECTL_2_4 2G_LNA2 [19] FECTL_2_5 5G_CR3 [21] FECTL_3_0 5G_PE3 [21] FECTL_3_1 5G_LNA3 [21] FECTL_3_2 FECTL_2_3 D19 FECTL_2_4 C18 FECTL_2_5 D20 FECTL_3_0 D21 FECTL_3_1 A14 FECTL_3_2 E10 B11 C24 D23 XTP8 XTP37 C XTP9 XTP1
PAGE 14
5 4 3 2 1 SKY85331-11 : Output power: +22 dBm @ 1.8% EVM, HT40, MCS9, 5 V Output power: +26 dBm @ 3% EVM, HT40, MCS7, 5 V PA_2G0 2.4G FEM CH0 (AX)6.8nH/0.6A/0805/5% 10 XC15 (AX)4.7uF/16V/0805/10% PA_2G0 20 PA_2G0 22 PA_2G0 23 PA_2G0 24 GND XR28 FECTL_0_4 FECTL_0_4 1 2G_PE0 2 XC22 (AX)0.1uF/16V/0402 XC20 (AX)0.1uF/16V/0402 Layout Notice : - Decoupling CAP should be placed before RES (AX)0R/0402/5% XC21 (AX)0.1uF/16V/0402 XC37 BPF_2A0 50 ohm 15 XC19 (AX)0.
PAGE 15
5 4 3 2 1 SKY85331-11 : Output power: +22 dBm @ 1.8% EVM, HT40, MCS9, 5 V Output power: +26 dBm @ 3% EVM, HT40, MCS7, 5 V PA_2G2 2.4G FEM CH2 10 XC59 (AX)4.7uF/16V/0805/10% PA_2G2 20 PA_2G2 22 PA_2G2 23 PA_2G2 24 BPF_2A2 50 ohm 15 BPF_2B2 50 ohm 13 GND FECTL_2_4 1 XC63 2G_PE2 2 XC55 (AX)0.1uF/16V/0402 XC60 (AX)0.1uF/16V/0402 GND (AX)0R/0402/5% 2G_PE2 (AX)1pF/50V/0.
PAGE 16
5 4 3 2 1 SKY85743-31 : Output power: +21 dBm, -43 dB DEVM, MCS11 Output power: +22 dBm, -40 dB DEVM, MCS11 Output power: +24 dBm, -35 dB DEVM, MCS9 PA_5G1 5G FEM CH1 XC32 XR103 is new part wihtout Draytek part number PA_5G1 Layout Notice : - Each Vcc pin needs to be individually decoupled. - VCC0, VCC1, VCC2, and VCC3 should NOT be shorted together at the device pins. XC147 is 6.3V voltage in REF design (AX)6.8nH/0.
PAGE 17
5 4 3 2 1 SKY85743-31 : Output power: +21 dBm, -43 dB DEVM, MCS11 Output power: +22 dBm, -40 dB DEVM, MCS11 Output power: +24 dBm, -35 dB DEVM, MCS9 PA_5G3 XR119 is new part wihtout Draytek part number D 5G FEM CH3 XC91 PA_5G3 Layout Notice : - Each Vcc pin needs to be individually decoupled. - VCC0, VCC1, VCC2, and VCC3 should NOT be shorted together at the device pins. XC147 is 6.3V voltage in REF design (AX)6.8nH/0.
PAGE 18
5 4 3 2 1 PWR_3V3_SLIC PWR_12V_SLIC PWR_3V3_SLIC PWR_12V_SLIC PWR_1V5_SLIC SLIC220 PWR_1V5_SLIC D D PWR_3V3_SLIC R16 (V)2.2K SLIC_RESET_M 8 SLIC_RESET_M R19 R15 C9 Null/2.
PAGE 19
5 4 3 2 1 SLIC220 R197 MRA_RR (V)750k,1% RINGA R196 4 (V)TISP6NTP2CDR 1 3 2 GND (V)4.7mH PWR_VNA 2 C138 (V)100nF MRA RINGA MRB RINGB 9 R184 MRB (V)TISP6NTP2CDR C13 (V)15nF (V)15nF C4 GND C15 1 R25 3PWR_VNB C129 (V)100nF (V)15nF C10 31 MTA (V)36R MTA_RR (V)750k,1% CMC2 6 GND GND R198 RINGB (V)36R V2 21 7 GND TIPA D (V)750k,1% R9 1 GND TIPA_L_1 43 29 V2 (V)PEF42078V 42 TIPA TIPB MTA MTB (V)15nF 2 4 RINGB_L 3 TIPB_L_1 (V)4.
PAGE 20
5 4 3 2 1 DCDC Type Dedicated DCDC = T0.2 Combined DCDC = T1.1 D D Move radiating parts (like switching regulators and coils, voice SLIC/coils,) far away from DSL-AFE. A distance (at least 5cm) between the reiating part and the DSL must be maintain. PWR_3V3_SLIC R194 SWD_E_1 2 14 SWDA PWR_12V_SLIC 3 (V)MMBT3904 SWD_B_1 VQ2 (V)ZX5T955GTA SWD_B_1 C134 (V)47nF R27 PWR_C_1 L9 PWR_C_1 ISENSA ISENSEA (V)0.
PAGE 21
5 4 3 2 1 DCDC Type Dedicated DCDC = T0.2 Combined DCDC = T1.1 D D Move radiating parts (like switching regulators and coils, voice SLIC/coils,) far away from DSL-AFE. A distance (at least 5cm) between the reiating part and the DSL must be maintain. PWR_3V3_SLIC 1 PWR_12V_SLIC SWD_E_2 2 R192 SWDB SWDB PWR_12V_SLIC (V)MMBT3904 VQ1 (V)47nF R3 (V)ZXTP2014G L3 GND C 14 SWD_B_2 SWD_B_2 C128 (V)0.
PAGE 22
5 4 3 2 1 U50A +3V3_DG GND R409 (6)4.7K A4 R410 NULL/4.7K B4 B5 D C392 (6)22PF GND R440 B1 B2 (6)0 CLKMODE RXA_P_DSL RXA_N_DSL CLKOUT_P CLKOUT_N RXB_P_DSL RXB_N_DSL XTAL1 XTAL2 RXC_P_DSL RXC_N_DSL Y3 (6)36MHz GND C393 (6)22PF TX_P_DSL TX_N_DSL XTAL-6C-SMD TEST_P_DSL TEST_N_DSL VDC_IN R441 A3 (6)6.
PAGE 23
5 4 3 2 1 U50C D D PWR_DIG_1V1_618C7 C9 C15 C21 C27 C28 C31 C36 C38 C41 C44 C5 PWR_IO_3V3_618B36 B40 B43 B45 C25 C A6 A22 A24 A34 A35 A51 A52 B32 B49 D1 D2 D3 D4 +3V3_DG FB10 PWR_IO_3V3_618 (6)FB/600ohm C399 C400 C401 C402 C403 C404 C407 C405 VDD1V1 VDD1V1 VDD1V1 VDD1V1 VDD1V1 VDD1V1 VDD1V1 VDD1V1 VDD1V1 VDD1V1 VDD1V1 VDDA1V5LCPLL VDDA1V5CLKD VDDA1V5FAST VDDA1V5DSL DVDDD2V5_L1 DVDDD2V5_L1 VDDA3V3_TEMP VDDA3V3XO VDDA3V3BGP VDDD1V1 VDDA3V3LCPLL VDDA3V3_RO DVDDD3V3_R1 DVDDD3V3_R1 DVDDD3V
PAGE 24
5 4 3 2 1 +3V3_DG 14V_LD U1907 R334 (6)10R 4 1 2 6 U1906B GND E2 E2 U1905B 3 4 5 VDSL2_LD_C0 VDSL2_LD_C1 VDSL2_LD_C2 R333 (6)10R 4 D C324 7 (6)100nF C0 C1 C2 VDD VDD_N VDD_P VDD NC NC NC LD_INS_P LD_INS_P CCM VSS EPAD FB26 8 9 17 18 16 10 C321 C322 C320 C319 (6)10nF (6)10nF (6)100nF (6)100nF (6)1uF GND GND GND GND C323 (6)FB/600ohm D GND 13 21 LD_INS_P_6 LD_INS_N_6 3 GND GND HYBRID_CTRL_2 LD_IN_N_6 LD_IN_N LD_OUT_N LD_FB_N C1 B1 TP131 1 1 (6)BCR08PN G
PAGE 25
5 4 Protection 3 2 RX Filter 14V_LD 1 RAP6 C_RXA_IN_P_6 CAP6 (VD)1.5nF (VD)390R RXA_P_6 41 RXA_N_6 41 RXB_P_6 41 RXB_N_6 41 RXC_P_6 41 RXC_N_6 41 C685 CAN6 C_RXA_IN_N_6 (VD)1.5nF 4 1 (VD)22uF25V D GND D11 (VD)DSL70/SOT143 RXA_TR_P_6 2 3 RXA_TR_N_6 (VD)1k,1% NULL/WS16P4SMA-B (VD)1k,1% RCN6 CCN6 C1_RXC_IN_N_6 (VD)680pF GND D RCP6 CCP6 C1_RXC_IN_P_6 (VD)680pF 2 1 14V_LD (VD)1k,1% RBN6 CBN6 C1_RXB_IN_N_6 (VD)1.
PAGE 26
5 4 3 GFAST_RXA_P 2 C352 (6)220pF R301 (6)33R C358 (6)220pF R354 (6)33R 1 R352 NULL/0R D D GFAST_RXA_N R368 GFAST_TR_P C368 C359 GFAST_RXB_P (6)82pF C364 (6)39pF L2056 (6)1.8uH R356 L2057 (6)2.2uH (6)0R (6)47pF G_RTA_P C369 R355 (6)470R NULL/1nF R358 (6)0R GND G_RTA_N C C363 (6)120pF T6 4 C362 6 7 1 8 C365 CMC3 G_CLINE_P 4 C688 (6)2.
PAGE 27
5 4 3 2 1 VDC_IN 1.15V for system 12V DC Power Input VDC_IN C152 1uF/50V/X7R for 350 core 112VIN1 2 S1 SK54 Co-layout L6 2 BC610RH6-B-3.0 C121 GND GND GND 2 R17 Null/0/1206 1 GND GND EC2 EC3 + + C1 1000pF PWR_12V_SLIC GND BST SW GND 5 NULL/118K R209 VIN EN R193 +3V3 (V)0/1206 R367 GND VDC_IN 1 FB 4 6 R205 120K C154 R208 3.92K/1% R204 PWR_12V_VRX618 R203 GND GND 10.5K/1% C156 + R1 R2 C151 0.
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5 4 3 2 1 VDC_IN DC to DC Boost 12V to 14V circuitry 1V for WAV654 VDC_IN If use SY7208C pwm the 270pF must be remove +3V3 XC102 (AX)1uF/50V/X7R D2 1 D SW NC GND (6)22.6K/1% GND 3 FB C292 Null/10uF R131 R132 Null/22k (6)SY7208CABC LMR62014/SY7208CABC XC100 GND GND VDD1V5_AX (6)1K/1% GND (AX)0.1uF 1 EN XR115(AX)10K BST GND FB 4 2 6 XR112 (AX)120K (AX)MP1655 GND XR111 XC104 XC105 (AX)2.74K/1%+ R1 XR113 R2 XC101 (AX)0.
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5 4 3 2 1 REVISION HISTORY Version Date List of Modification Page 2020-12-01 Ian D D V0A 2020-12-10 2.4GHz FEM (152-5331900-00G,SKY85331-11) : 1. Add XU31, XU33 2. Remove XC12, XC13, XC10, XC11 3. Null XR101, XR88, XU30, XU32 4. Place XR137, XR136 5. Remove XR146, XR149, XR142, XR145 5GHz FEM (152-5743900-00G,SKY85743-31) : 1. Add XU51, XU53 for co-layout with XU52, XU54 2. Remove XR117, XR113, XC16, XC17 3. Remove XR118, XR129, XC181, XC182 4. Place XR11, XR12 6. Null XU61, XR10, XR135 7.
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5 4 3 2 1 BOM Difference V2765ax V2765Vax D (VD) (V) (5) (PD) (AX) (NPD) (AX_LTE) V NULL V NULL V V NULL V V V NULL V V NULL D C C B B A A Title Size B Date: 5 4 3 2 BOM Difference Document Number Rev 6B V2766AX Thursday, July 21, 2022 Sheet 1 98 of 27