Product Diagram
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PHY addr range=b'000~111 setting by user
LED mode=2
LED mode[1]
(Inverter)
(Inverter)
Mini GBIC
Reserved for if MAU require
Close to SFP
Near IP1001C
Near Fiber MAU
Near Fiber MAU
As close to U1 (IP1001C) as possible
Phy_addr[1]
Drive[1]
Drive[0]
RGMII_dly_rxc
RX_Delay[1]
TX_Delay[1]
Phy_addr[2]
Select SFP to low
active
Phy_addr[0]
G1 PHY addr=b'111
(Normal)
(Inverter)
(Inverter)
Trace width 40mils
DVDD10 & AVDD10 must
be separated by a bead or
0R.
Trace width 40 mils
LED mode[0]
Reset Circuit
25MHz Clock
Select RGMII
For EMI
3V3
3V3
3V3
VDDIO
VDDIOREG
3V3
VDDIO
GND
3V3
3V3
3V3
3V3
GND
GND
+3V3
Fiber-RESETB
wMDIO
wMDC
RXCTL
RXCLK
RXD0
RXD1
RXD2
RXD3
TXCLK
TXD0
TXD1
TXD2
TXD3
TXCTL
SFP_I2C_DATA
SFP_I2C_CLK
SFP_MOD_DET
SFP_RX_LOS_1 [2]
PHY_INTn
Title
Size Document Number Rev
Date: Sheet of
IP1001CD2V01
6C
V2135AX
B
11 26Friday, February 11, 2022
Title
Size Document Number Rev
Date: Sheet of
IP1001CD2V01
6C
V2135AX
B
11 26Friday, February 11, 2022
Title
Size Document Number Rev
Date: Sheet of
IP1001CD2V01
6C
V2135AX
B
11 26Friday, February 11, 2022
R46
0R
OR10 NULL/130R
FR26
(F)10K
FC40
(F)0.1uF_0402
FR40
Null/4.7K
OR11 NULL/82R
FR13 10K
FR33
NULL/10K
FC19 (F)0.1uF
FR22
NULL/10K
FC31 (F)22uF
FR9
(F)0R
12
FR2 (F)51R
FR32
(F)10K
OR3(F)1K
FR34
(F)10K
FC36 (F)0.1uF
FC26 (F)1nF
OR9 NULL/82R
OR610K
OR12 NULL/130R
FB11
(F)120ohm@100MHz/2A
OR1
(F)10K
FR20
(F)10K
FC8 (F)4.7uF
FR41
0
FC21 (F)0.1uF
OC1
(F)10nF/X7R
FC35 (F)1nF
FR6 (F)33ohm,Bead
FR25
(F)10K
FB9
(F)120ohm@100MHz/2A
FC20 (F)22uF
FC15 (F)4.7uF
FR16
NULL/10K
OC4
(F)10nF/X7R
FR37
0
E-Pad GND
G1U1
(F)IP1001C
QFN68-0.4/EPAD
LED[3]/LED_mode_n[1]
33
LED[4]/SERDES_set
34
LED[5]/PHY_addr0
35
LED[6]/PHY_addr1
36
LED[8]/OP_mode
38
LED[9]/XMII_pin_reorder
39
AVSS10
42
MDI[1]+
43
MDI[1]-
44
ISET
55
MDI[2]+
46
MDI[2]-
47
MDI[0]+
40
MDI[0]-
41
AVDD10
48
MDI[3]+
49
MDI[3]-
50
AVDD33
51
SWR_VOUT
52
AVSS
53
AVDD33
54
TXD1/2
21
AVDD10
56
X1(XTLI)
58
NC
57
NC
1
NC
68
X2(XTLO)
59
AVDD33
60
SON
61
SOP
62
AVDD10
63
TXD0/3
20
TXCLK
19
SIP
64
SIN
65
1588_EVENT
4
NC
3
RESET
67
NC
2
INT
8
DVDD10
9
NC
10
MDC
7
RXD0/3//RGMII_dirve1
12
RXD1/2//RGMII_dirve0
13
RXD2/1//RGMII_dly_rx
14
RXD3/0//RGMII_dly_tx
15
VDDIO_IN1
16
MDIO
6
1588_PPS/RGMII_set
5
RX_CTL/RGMII_dly_rxc
11
RXCLK/PHY_addr2
17
TXD2/1
22
E-Pad GND
69
VDDIO_IN2
27
TXD3/0
23
DVDD10
24
TX_CTL
25
VDDIO_REG(LDO_OUT 1.8/2.5V )
26
DVDD10
32
EE_DAT
28
EE_CLK/AZ enable
29
LED[1]/LED_CLK
30
LED[2]/LED_DAT/LED_mode_n[0]
31
LED[7]/FX_CFG
37
AVDD33
45
SD
66
NC
18
OR8 NULL/130R
OC12 1nF/2KV/1206
FR4 (F)51R
FR3 (F)51R OR13 NULL/82R
FC16 (F)4.7uF
FR8
(F)0R
FC22 (F)22uF
FC37 (F)0.1uF_0402
FC34 (F)22uF
FC32 (F)1nF
OC7 (F)0.1uF
OR41K
FC13 (F)4.7uF
OR7 NULL/82R
TP14
EEDAT
G1L1
(F)4.7uH / GNR2512
FC3 (F)0.1uF
FR31
NULL/10K
FR5 (F)51R
FC38 (F)0.1uF_0402
FR30
NULL/10K
FB8
(F)120ohm@100MHz/2A
OR510K
FR21
NULL/10K
FB10
(F)120ohm@100MHz/2A
FC7 (F)0.1uF
FR38
0
TP15
EECLK
FJ1
(F)SFP-Slot
VeeTX
20
TX_Fault
2
TX_DIS
3
MOD_DEF2
4
MOD_DEF1
5
MOD_DEF0
6
RATE_SEL
7
Rx_LOS
8
VeeRX
9
VeeRX
10
VeeRX
14
RD-
12
RD+
13
VeeRX
11
VccRX
15
VccTX
16
VeeTX
17
TD+
18
TD-
19
VeeTX
1
FC39
(F)0.1uF_0402
FR23
(F)10K
OR14 NULL/130R
OC10 (F)10uF
OC2
(F)10nF/X7R
FC14 (F)4.7uF
FR39
(F)4.7K
OC8 (F)10uF
FC1
(F)0.1uF
FC9 (F)0.1uF
FC42
NULL/10pF
FC33 (F)0.1uF
FC4 (F)0.1uF
FC10
(F)4.7uF
FX1
(F)25MHz
NC
4
X1
1
NC
2
X2
3
FR18
NULL/10K
OL1 70ohm@100MHz/4A
FJ2
NULL/SFP Module
(F)SFP Case
GND
1
GND
2
GND
3
GND
4
GND
5
GND
6
GND
7
GND
8
GND
9
GND
10
GND
20
GND
19
GND
18
GND
17
GND
16
GND
15
GND
14
GND
13
GND
12
GND
11
FR24
NULL/10K
OC5 1nF/2KV/1206
OC11 (F)0.1uF
FC25 (F)22uF
OL2 70ohm@100MHz/4A
FR17
NULL/10K
FR36
0
OC6 (F)10uF
FR15
NULL/10K
FR1 (F)51R
FC27 (F)0.1uF
FC18
(F)18pF
FC5
(F)0.1uF
FC2 (F)0.1uF
FC41 (F)0.1uF_0402
OC3
(F)10nF/X7R
OC9 (F)0.1uF
FR35 1.5K
FC17
(F)18pF
FR19
NULL/10K
C465
(F)100nF
FR7 (F)6.19K/1%
TXCLK
TXD0
TXD1
TXD2
TXD3
TXCTL
DVDD10
LED3
LED2
VDDIO_OUT
VDDIOREG
REG10
SIP
RD-
SOP
SIN RD-
RD+
VR
TD+
SON TD-
SD
LED2
LED3
Addr0
Addr1
AVDD33
VDDIO
REG10
VDDIOREG
AVDD33
RXCTL
RXD1
RXD2
RXD3
RXD0
RXCLK
Addr0
Addr1
AVDD10
DVDD10
VDDIO
VDDIO_OUT
SIN
X1
X2
AVDD33
AVDD33
SIP
AVDD10
SOP
SON
AVDD10
SD_IC
X1
X2
RESET
SET
REG10
RESETB
AVDD33
AVDD10
MDC
PHY_INTn
VDDIO
RXCTL
RXD0
RXD1
RXD2
RXD3
RXCLK
DVDD10
MDIO
RD+
TD+
TD-
MOD_DEF2
MOD_DEF1
MOD_DEF0
RATE_SELECT
MOD_DEF1
MOD_DEF0
MOD_DEF2
VT
SD
PHY_INTn
SD_IC