5 4 3 SPI FLASH NAND FLASH DDR3 SDRAM 2Mbit 128MB 256MB 2 TRAN GPIO DDR 1 Eth-RJ45(option) EBU D D PoE-PD INT_GPHY-TP6F PCIE3 INT_GPHY_TP2 INT_GPHY_TP3 INT_GPHY_TP4 INT_GPHY_TP5 TRAN TRAN 4port giga LAN USB_0 PCIE1 +5V USB_1 USB2.0 USB Host Jack USB2.
5 4 3 2 1 U5A NFLASH_IO[7..0] NFLASH_IO[7..0] GPHY 12 12 12 12 12 12 12 12 D 1.100 ohm characteristic impedance control for TPI differential signal routing. Keep the reference plane of signal continuous. 2.The TPI signals should be routed along with a solid reference GND plane to have precise impedance matching. It will be good to route all the trace in one single layer. If layer interchanged is necessary for trace routing, minimizing via count is absolutely needed.
5 4 3 2 1 U5B DDR_ADDR1 NETRN5_3 NETRN5_2 NETRN5_1 NETR126_2 NETRN5_3 NETRN8_3 NETRN9_4 NETRN6_4 NETRN6_4 NETRN6_3 NETRN6_2 NETRN6_1 NETRN9_4 NETRN9_2 NETRN6_2 NETRN8_4 NETRN6_1 NETRN8_2 NETRN9_3 NETRN9_2 NETRN9_1 NETRN7_4 NETRN7_3 NETRN6_3 NETRN7_2 NETR127_2 K2 A5 K3 B1 A4 H3 B3 G1 B2 J3 C3 D3 D2 G2 E3 A2 NETRN4_4 NETRN9_3 NETRN5_1 L3 C4 K1 NETR324_2 NETR311_2 H2 J2 NETRN5_2 D DDR_ADDR2 DDR_ADDR0 DDR_BA2 DDR_ADDR5 DDR_ADDR13 DDR_ADDR7 DDR_ADDR9 DDR_ADDR4 DDR_BA1 DDR_ADDR6 DDR_CAS 6.
5 4 3 VDD115 C182 C235 C228 C229 C219 C194 C195 C196 C197 C199 C198 C200 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF GND VDD115 D C248 10uF C216 C224 C223 C232 C238 C237 C250 100nF 100nF100nF100nF100nF100nF100nF C249 C257 C256 C255 100nF 100nF 100nF 100nF GND VDDL_1V15 C220 10nF C221 C222C231 C230 C236 100nF 10nF 10nF100nF 100nF VDDL_1V15 GND VDDH_3V3 VDD33 C253 C243 C261 C218 C193 C192 10nF10nF 10nF 100nF 100nF 100nF VDDH_3V3 C171 C202 10nF 10nF C246 100nF C245 100nF VDD3
4 3 2 1 D D U5D B23 B22 A22 B21 [9] [9] USB_DP0 USB_DM0 USB_DP0 USB_DM0 OC_SENSE1 [9] D22 C22 R101 200R,1% GND OC_SENSE1 NETR10_1 D23 AC7 A20 A19 C19 B19 USB_DP1 [9] [9] USB_DP1 USB_DM1 C C20 B20 USB_DM1 OC_SENSE2 [9] R102 GND 200R,1% OC_SENSE2 C21 AC8 PCIe1 P_cP1 P_cN1 P_tP1 P_tN1 P_rP1 P_rN1 USB0 USBtP0 USBtN0 USBrP0 USBrN0 DP0 DM0 RREF1 RREF0 OC_SC0 PCIe2 P_cP2 P_cN2 P_tP2 P_tN2 P_rP2 P_rN2 USB1 USBtP1 USBtN1 RREF2 USBrP1 USNrN1 PCIe3 P_cP3 P_cN3 P_tP3 P_tN3 P_rP3 P_
5 4 3 2 1 D D U5E AA17 AB17 AC16 AC17 AB18 AB15 C AA15 AC14 AB14 AB16 AC13 AB13 AB12 AA13 AA14 Trace capacitance for BBIO interface must be below 10pF! Recommend the maximum length should be under 3 inch.
5 4 3 2 1 U5F for 654 EVB FW [16] RST_TO_DEFAULT_1 SLIC_RESET RST_TO_DEFAULT_AXE AB3 AA5 Y11 Y18 AB8 AA8 Y9 Y10 AB5 AB4 AB6 AA7 USB1_CTRL GPIO3 GPIO4 TP8 [12] D SLIC_CLK GPIO5 GPIO6 USB2_CTRL 0/0402 [8] SPI_Flash_CS1 [8,10] SPI_DIN [8,10] SPI_DOUT [8,10] SPI_CLK +3V3 RESET_IN R53 GPIO18 GPIO19 R52 C17 +3V3 NULL/470pF [12] GND 47k,1% [8,10] GPIO17_RST [8,10] GPIO18_RST GPIO17 DGSP_RST C16 NULL/10uF GND C19 SLIC_TX NULL/33pF GND N.M.
5 4 3 2 1 NFLASH_IO[7..0] D [2] NFLASH_IO[7..
4 3 2 1 !!Note: The PCB layout of the differential signal DP and DM should have 90 ohm differential impedance, and keep the trace length below 1 inch if possible. USB_VOUT_B Bottom USB2.0 4 TOP B Bottom A USB Device Connector 4 Port A EC10 + (USB)560uF/6.3V C105 R151 (USB)Dual_USB_Connector GND VCC DATADATA+ GND CH1 USB_DM1 NULL_CM-CHOKE USB_DP1 10 J7A 9 GND (USB)0.1uF GND (USB)0R 1 2 3 4 C95 R150 USB_DM1 6 USB_DP1 6 C90 (USB)0R Null/5pF Null/5pF USB_VOUT_A TOP USB2.
5 4 3 2 1 LED1 SOUT23 ACT R24 2 NULL/150ohm 1 C31 LED colay 100nF 16 GND D [7] LED_D [7] LED_SH [7] LED_ST [7] POR_OUT_4 LED_D LED_SH LED_ST POR_OUT_4 14 11 12 10 13 8 LED_D <--> GPIO5 LED_ST <--> GPIO4 LED_SH <--> GPIO6 R83 NULL/0R GND GreenNULL/SLED_0603_G +3V3 GND LED2 U17 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7 DS SHCLK STRCLK MR OE 15 1 2 3 4 5 6 7 9 SOUT23 SOUT22 SOUT21 SOUT20 SOUT15 SOUT20 R23 1 YELLOW NULL/150ohm 1 2 R28 3 GREEN NULL/120ohm 3 4 WAN SOUT18 2 GND 4 G
8 7 6 5 4 C70 GND GND 3 3 GTP0_DN GTP0_DP 3 3 GTP0_CN GTP0_CP 3 3 GTP0_BN GTP0_BP 3 3 GTP0_AN GTP0_AP R130 R124 NULL/16K NULL/16K 3 T3A C71 68pF GTP0_DN GTP0_DP GND GTP0_CN GTP0_CP GND C293 68pF GTP0_BN GTP0_BP GND C65 68pF GTP0_AN GTP0_AP GND C286 68pF 1 2 3 4 5 6 7 8 9 10 11 12 TCT5 TD5+ TD5TCT6 TD6+ TD6TCT7 TD7+ TD7TCT8 TD8+ TD8- 48 47 46 45 44 43 42 41 40 39 38 37 C68 0.1uF/100V/0805 R129 C66 0.1uF/100V/0805 R123 C64 0.1uF/100V/0805 R121 C61 0.
4 3 2 PoE-PD (PD)SCD310/3A/100V PD2 (PD)SCD310/3A/100VPD10 (PD)SCD310/3A/100V PD_CMT_B PD_CMT_C PD_CMT_D (PD)SCD310/3A/100V PD_CMT_D 22 PD_CMT_B PD_CMT_C PC15 (PD)1000PF 2KV PD14 (PD)SCD310/3A/100V PD3 PC16 (PD)0.1uF/100V/0805 GND PC17 (PD)0.1uF/100V/0805 PD9 (PD)SMAJ58A/58V/400W PC8 (PD)1nF/2KV/1206 PC11 (PD)1nF/2KV/1206 PC13 (PD)2.2nF/2KV/1812 48V_V- 11 22 POE_GND CO-LAY PD13 2 GND PL2 (PD)3.3uH/1.
4 B NULL/10K NULL/10K FR17 FR18 FR19 NULL/10K FR20 (F)10K FR21 NULL/10K NULL/10K FR22 NULL/10K FR23 FR24 (F)10K FR25 (F)10K VDDIOREG NULL/10K FR16 NULL/10K LED mode[0] LED mode=2 NULL/10K LED2 FR33 (Inverter) (F)10K LED mode[1] LED3 FR34 (Inverter) 70ohm@100MHz/4A VR 15 14 OC3 (F)10nF/X7R RD+ 13 OC4 RD- 12 TD+ TX_DIS VeeTX MOD_DEF2 VccTX MOD_DEF1 VccRX MOD_DEF0 VeeRX RATE_SEL RD+ Rx_LOS RD- VeeRX AVDD10 FC10 (F)4.
5 4 3 2 WAVE654 PCIE / GPIO / SPI WAVE654 POWER XC167 XU14A A45 D49 FSYS_OUT_P E36 XTP13 FSYS_IN_N E37 FSYS_IN_P D51 XTP12 XTP11 GPIO13 GPIO14 GPIO15 FSYS_OUT2_N FSYS_OUT2_P FSYS_IN_N XTAL1 FSYS_IN_P XTAL2 VDDRF1V5HBANT3 VDD0V9_9 VDDRF1V5LBANT0 VDD0V9_10 VDDRF1V5LBANT1 VDD0V9_11 VDDRF1V5LBANT2 VDD0V9_12 VDDRF1V5LBANT3 VDD0V9_13 VDDRF1V5RXANT0 VDD0V9_14 VDDRF1V5RXANT1 VDD0V9_15 VDDRF1V5RXANT2 VDD0V9_16 VDDRF1V5RXANT3 BB3V3PLL (AX)0R/0402/5% GND GND XC135 XC112 GND GN
4 [18] FECTL_0_4 2G_LNA0 [18] FECTL_0_5 [20] FECTL_1_0 5G_PE1 [20] FECTL_1_1 5G_LNA1 [20] FECTL_1_2 FECTL_0_3 C6 FECTL_0_4 C7 FECTL_0_5 D7 FECTL_1_0 C9 FECTL_1_1 D10 FECTL_1_2 C10 A11 C12 D12 E4 D17 E5 2G_CR2 [19] FECTL_2_3 2G_PE2 [19] FECTL_2_4 2G_LNA2 [19] FECTL_2_5 5G_CR3 [21] FECTL_3_0 5G_PE3 [21] FECTL_3_1 5G_LNA3 [21] FECTL_3_2 FECTL_2_3 D19 FECTL_2_4 C18 FECTL_2_5 D20 FECTL_3_0 D21 FECTL_3_1 A14 FECTL_3_2 E10 B11 C24 D23 XTP8 XTP37 C XTP9 XTP1
5 4 3 2 1 SKY85331-11 : Output power: +22 dBm @ 1.8% EVM, HT40, MCS9, 5 V Output power: +26 dBm @ 3% EVM, HT40, MCS7, 5 V PA_2G0 2.4G FEM CH0 (AX)6.8nH/0.6A/0805/5% 10 XC15 (AX)4.7uF/16V/0603/10% PA_2G0 20 PA_2G0 22 PA_2G0 23 PA_2G0 24 GND XR28 FECTL_0_4 FECTL_0_4 1 2G_PE0 2 XC22 (AX)0.1uF/16V/0402 XC20 (AX)0.1uF/16V/0402 Layout Notice : - Decoupling CAP should be placed before RES (AX)0R/0402/5% XC21 (AX)0.1uF/16V/0402 XC37 BPF_2A0 50 ohm 15 XC19 (AX)0.
5 4 3 2 1 SKY85331-11 : Output power: +22 dBm @ 1.8% EVM, HT40, MCS9, 5 V Output power: +26 dBm @ 3% EVM, HT40, MCS7, 5 V PA_2G2 2.4G FEM CH2 10 XC59 (AX)4.7uF/16V/0603/10% PA_2G2 20 PA_2G2 22 PA_2G2 23 PA_2G2 24 BPF_2A2 50 ohm 15 BPF_2B2 50 ohm 13 GND FECTL_2_4 1 XC63 2G_PE2 2 XC55 (AX)0.1uF/16V/0402 XC60 (AX)0.1uF/16V/0402 GND (AX)0R/0402/5% 2G_PE2 (AX)1pF/50V/0.
5 4 3 2 1 SKY85743-31 : Output power: +21 dBm, -43 dB DEVM, MCS11 Output power: +22 dBm, -40 dB DEVM, MCS11 Output power: +24 dBm, -35 dB DEVM, MCS9 PA_5G1 5G FEM CH1 XC32 XR103 is new part wihtout Draytek part number PA_5G1 Layout Notice : - Each Vcc pin needs to be individually decoupled. - VCC0, VCC1, VCC2, and VCC3 should NOT be shorted together at the device pins. XC147 is 6.3V voltage in REF design (AX)6.8nH/0.
5 4 3 2 1 SKY85743-31 : Output power: +21 dBm, -43 dB DEVM, MCS11 Output power: +22 dBm, -40 dB DEVM, MCS11 Output power: +24 dBm, -35 dB DEVM, MCS9 PA_5G3 XR119 is new part wihtout Draytek part number D 5G FEM CH3 XC91 PA_5G3 Layout Notice : - Each Vcc pin needs to be individually decoupled. - VCC0, VCC1, VCC2, and VCC3 should NOT be shorted together at the device pins. XC147 is 6.3V voltage in REF design (AX)6.8nH/0.
5 4 3 2 1 PWR_3V3_SLIC PWR_12V_SLIC PWR_3V3_SLIC PWR_12V_SLIC PWR_1V5_SLIC SLIC220 PWR_1V5_SLIC D D PWR_3V3_SLIC R16 (V)2.2K SLIC_RESET_M 8 SLIC_RESET_M R19 R15 C9 Null/2.
5 4 3 2 1 DCDC Type Dedicated DCDC = T0.2 Combined DCDC = T1.1 D D Move radiating parts (like switching regulators and coils, voice SLIC/coils,) far away from DSL-AFE. A distance (at least 5cm) between the reiating part and the DSL must be maintain. PWR_3V3_SLIC 1 PWR_12V_SLIC SWD_E_2 2 14 R192 SWDB SWDB 3 PWR_12V_SLIC V5 (V)160R (V)MMBT3904 VQ1 (V)47nF R3 (V)ZXTP2014G L3 (V)0.
5 4 3 2 1 VDC_IN 1.15V for system 12V DC Power Input VDC_IN C152 1uF/50V/X7R for 350 core S1-1 Co-layout L6 1 2 220ohm/bead C121 2 1 2 GND GND 220ohm/bead EC3 + + C1 1000pF GND PWR_12V_SLIC 5 BST EN NULL/118K R193 FB +1V15 @ Max 3.5A 4 6 R205 120K C154 R208 3.92K/1% R204 GND 10.5K/1% R203 GND GND C156 + R1 R2 C151 0.1uF C158 + GND GND VDC_IN 0R SENSE- [7] C2 1 VIN GND FB 6 R234 R229 40.2K C161 31.
5 4 3 2 1 SLIC220 R197 MRA_RR (V)750k,1% RINGA R196 4 (V)TISP6NTP2CDR 1 3 2 GND (V)4.7mH PWR_VNA 2 C138 (V)100nF MRA RINGA MRB RINGB 9 R184 MRB (V)TISP6NTP2CDR C13 (V)15nF (V)15nF C4 GND C15 1 R25 3PWR_VNB C129 (V)100nF (V)15nF C10 31 MTA (V)36R MTA_RR (V)750k,1% CMC2 6 GND GND R198 RINGB (V)36R V2 21 7 GND TIPA D (V)750k,1% R9 4RINGB_L 1 GND TIPA_L_1 43 29 V2 (V)PEF42078V 42 TIPA TIPB MTA MTB (V)15nF 3TIPB_L_1 2 (V)4.
5 4 3 2 1 VDC_IN 1V for WAV654 VDC_IN GND GND XR114 VDC_IN (AX)0.1uF 1 4 BST 2 SW 5 EN 6 FB XR112 (AX)120K XR113 (AX)10K/1% GND GND XC103 + + GND (AX)22uF/10V (AX)MP1655 GND XC104 XC105 (AX)2.74K/1%+ R1 R2 XC101 (AX)0.1uF XR111 (AX)10uF/10V XR115(AX)10K VDD1V_AX D VIN GND NULL/118K +1V @ Max 3.5A (AX)4.7uH/4A XL15 (AX)10R/1% XU19 (AX)22uF/10V VDD1V5_AX XR116 XC99 GND 270uF/16V D XC100 3 + (AX)4.
5 4 3 2 1 DCDC Type Dedicated DCDC = T0.2 Combined DCDC = T1.1 D D Move radiating parts (like switching regulators and coils, voice SLIC/coils,) far away from DSL-AFE. A distance (at least 5cm) between the reiating part and the DSL must be maintain. PWR_3V3_SLIC R194 SWD_E_1 2 14 SWDA PWR_12V_SLIC 3 (V)MMBT3904 SWD_B_1 VQ2 (V)ZX5T955GTA SWD_B_1 C134 (V)47nF R27 PWR_C_1 L9 PWR_C_1 ISENSA ISENSEA (V)0.
5 4 3 2 1 REVISION HISTORY Version Date List of Modification Page 1. Remove VRX518 circuit 2. Add EWAN circuit 3. Add IP1001 circuit 2021-02-02 Ian D D V6A 2020-12-10 V6B 2021-06-16 2.4GHz FEM (152-5331900-00G,SKY85331-11) : 1. Add XU31, XU33 2. Remove XC12, XC13, XC10, XC11 3. Null XR101, XR88, XU30, XU32 4. Place XR137, XR136 5. Remove XR146, XR149, XR142, XR145 5GHz FEM (152-5743900-00G,SKY85743-31) : 1. Add XU51, XU53 for co-layout with XU52, XU54 2. Remove XR117, XR113, XC16, XC17 3.
5 4 3 2 1 BOM Difference V2765ax V2765Vax D (VD) (V) (5) (PD) (AX) (NPD) (AX_LTE) V NULL V NULL V V NULL V V V NULL V V NULL D C C B B A A Title Size B Date: 5 4 3 2 BOM Difference Document Number Rev 6C V2135AX Friday, January 28, 2022 Sheet 1 98 of 26
